{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "IBM", "item": "https://www.patentleaderboard.com/company/ibm"}, {"@type": "ListItem", "position": 3, "name": "Warren E. Maule", "item": "https://www.patentleaderboard.com/inventor/fl:wa_ln:maule-1"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
WM

Warren E. Maule — 185 Patents

IBM: 180 patents #200 of 70,183Top 1%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
Cedar Park, TX: #3 of 1,158 inventorsTop 1%
Texas: #113 of 125,132 inventorsTop 1%
Overall (All Time): #4,037 of 4,157,543Top 1%
185 Patents All Time
Warren E. Maule has been granted 185 US patents while listed as an inventor at IBM. The first was granted in 1981 and the most recent in July 2023. Warren E. Maule ranks #4,037 of 4,157,543 US inventors in our database (top 0.10%). Patent records list Warren E. Maule in Cedar Park, TX, US.

Patents per Year

Patents granted per year, 1981 to 2023Bar chart with a peak of 18 patents in 2011.peak 181981: 1 patents19811984: 1 patents1994: 1 patents1996: 1 patents19961997: 1 patents1998: 5 patents1999: 6 patents19992000: 3 patents2001: 5 patents2002: 1 patents20022003: 2 patents2004: 1 patents2006: 1 patents20062007: 4 patents2008: 10 patents2009: 15 patents20092010: 10 patents2011: 18 patents2012: 14 patents20122013: 4 patents2014: 8 patents2015: 6 patents20152016: 7 patents2017: 14 patents2018: 12 patents20182019: 11 patents2020: 11 patents2021: 7 patents20212022: 1 patents2023: 4 patents2023

Issued Patents All Time

Showing 1–25 of 185 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11698842 Efficient and selective sparing of bits in memory systems Stephen P. Glancy, Kyu-hyoun Kim, Kevin M. Mcilvain 2023-07-11 $24,707,000
11593196 Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel Kevin M. Mcilvain, Stephen P. Glancy, Kyu-hyoun Kim, Edgar R. Cordero 2023-02-28 $9,133,000
11587600 Address/command chip controlled data chip address sequencing for a distributed memory buffer system Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more 2023-02-21 $5,683,000
11586360 Hybrid memory mirroring using storage class memory Peter J. Heyrman, David A. Larson Stanton, Adam J. McPadden 2023-02-21 $5,683,000
11264077 Redundant voltage regulator for memory devices Brian J. Connolly, Kyu-hyoun Kim 2022-03-01 $6,542,000
11200112 Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel Kevin M. Mcilvain, Stephen P. Glancy, Kyu-hyoun Kim, Edgar R. Cordero 2021-12-14 $4,192,000
11182262 Efficient and selective sparing of bits in memory systems Stephen P. Glancy, Kyu-hyoun Kim, Kevin M. Mcilvain 2021-11-23 $2,653,000
11037619 Using dual channel memory as single channel memory with spares Kyu-hyoun Kim, Kevin M. Mcilvain, Saravanan Sethuraman 2021-06-15 $4,393,000
11017875 Tracking address ranges for computer memory errors John S. Dodson, Marc A. Gollub, Brad W. Michael 2021-05-25 $5,474,000
10971246 Performing error correction in computer memory John S. Dodson, Marc A. Gollub, Brad W. Michael 2021-04-06 $3,234,000
10937485 Redundant voltage regulator for memory devices Brian J. Connolly, Kyu-hyoun Kim 2021-03-02 $2,720,000
10901839 Common high and low random bit error correction logic James A. O'Connor, Barry M. Trager, Brad W. Michael, Marc A. Gollub, Patrick J. Meaney 2021-01-26 $1,788,000
10824504 Common high and low random bit error correction logic James A. O'Connor, Barry M. Trager, Marc A. Gollub, Brad W. Michael, Patrick J. Meaney 2020-11-03 $4,313,000
10747442 Host controlled data chip address sequencing for a distributed memory buffer system Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more 2020-08-18 $3,155,000
10671497 Efficient and selective sparing of bits in memory systems Stephen P. Glancy, Kyu-hyoun Kim, Kevin M. Mcilvain 2020-06-02 $2,290,000
10628248 Autonomous dram scrub and error counting Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Tony E. Sawan 2020-04-21 $2,793,000
10613951 Memory mirror invocation upon detecting a correctable error Marc A. Gollub, Patrick J. Meaney 2020-04-07 $1,846,000
10606713 Using dual channel memory as single channel memory with command address recovery Kyu-hyoun Kim, Kevin M. Mcilvain, Saravanan Sethuraman 2020-03-31 $1,667,000
10606692 Error correction potency improvement via added burst beats in a dram access cycle Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Patrick J. Meaney, James A. O'Connor +1 more 2020-03-31 $1,667,000
10592332 Auto-disabling DRAM error checking on threshold Edgar R. Cordero, Marc A. Gollub, Lucas W. Mulkey, Anuwat Saetow 2020-03-17 $1,423,000
10546628 Using dual channel memory as single channel memory with spares Kyu-hyoun Kim, Kevin M. Mcilvain, Saravanan Sethuraman 2020-01-28 $1,679,000
10534545 Three-dimensional stacked memory optimizations for latency and power Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Kirk D. Peterson, Sridhar H. Rangarajan, Saravanan Sethuraman 2020-01-14 $2,827,000
10528288 Three-dimensional stacked memory access optimization Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Kirk D. Peterson, Sridhar H. Rangarajan, Saravanan Sethuraman 2020-01-07 $1,754,000
10497409 Implementing DRAM row hammer avoidance Charles A. Kilmer, Anil B. Lingambudi, Diyanesh Babu C. Vidyapoornachary 2019-12-03 $6,493,000
10468088 Redundant voltage regulator for memory devices Brian J. Connolly, Kyu-hyoun Kim 2019-11-05 $4,028,000