Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11687254 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2023-06-27 |
| 11587600 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more | 2023-02-21 |
| 11379123 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2022-07-05 |
| 11099601 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt | 2021-08-24 |
| 10976939 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2021-04-13 |
| 10771068 | Reducing chip latency at a clock boundary by reference clock phase adjustment | Steven R. Carlough, Michael W. Harper, Michael B. Spear, Gary A. Van Huben | 2020-09-08 |
| 10747442 | Host controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more | 2020-08-18 |
| 10740031 | Interface scheduler for a distributed memory system | Jie Zheng, Stephen J. Powell, Steven R. Carlough | 2020-08-11 |
| 10698440 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt | 2020-06-30 |
| 10642535 | Register access in a distributed memory buffer system | Steven R. Carlough, Markus Cebulla, Logan I. Friedman, Patrick J. Meaney, Walter Pietschmann +2 more | 2020-05-05 |
| 10534555 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2020-01-14 |
| 10489069 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2019-11-26 |
| 10393805 | JTAG support over a broadcast bus in a distributed memory buffer system | Logan I. Friedman, Nicholas Rolfe, Steven R. Carlough, Gary A. Van Huben, Markus Cebulla +1 more | 2019-08-27 |
| 10395698 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more | 2019-08-27 |
| 10353606 | Partial data replay in a distributed memory buffer system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Jie Zheng, Gary A. Van Huben | 2019-07-16 |
| 10162773 | Double data rate (DDR) memory read latency reduction | Steven R. Carlough, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt | 2018-12-25 |
| 10078461 | Partial data replay in a distributed memory buffer system | Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Jie Zheng, Gary A. Van Huben | 2018-09-18 |
| 8898504 | Parallel data communications mechanism having reduced power continuously calibrated lines | Steven J. Baumgartner, Frank D. Ferraiolo, Michael B. Spear | 2014-11-25 |