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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JD

John S. Dodson — 24 Patents

IBM: 24 patents #4,444 of 70,183Top 7%
Austin, TX: #1,344 of 18,064 inventorsTop 8%
Texas: #5,446 of 125,132 inventorsTop 5%
Overall (All Time): #168,038 of 4,157,543Top 5%
24 Patents All Time
John S. Dodson has been granted 24 US patents while listed as an inventor at IBM. The first was granted in 2001 and the most recent in October 2024. John S. Dodson ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list John S. Dodson in Austin, TX, US.

Patents per Year

Patents granted per year, 2001 to 2024Bar chart with a peak of 5 patents in 2019.peak 52001: 4 patents20012002: 3 patents20022003: 3 patents20032004: 1 patents20042015: 2 patents20152016: 2 patents20162019: 5 patents20192020: 1 patents20202021: 2 patents20212024: 1 patents2024

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12118236 Dynamically allocating memory controller resources for extended prefetching Eric E. Retter, Lilith Hale, Brad W. Michael 2024-10-15 $17,235,000
11017875 Tracking address ranges for computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2021-05-25 $5,474,000
10971246 Performing error correction in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2021-04-06 $3,234,000
10649511 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd J. Rosedahl +3 more 2020-05-12 $2,725,000
10353669 Managing entries in a mark table of computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-07-16 $4,107,000
10338999 Confirming memory marks indicating an error in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-07-02 $3,331,000
10317964 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd J. Rosedahl +3 more 2019-06-11 $1,829,000
10304560 Performing error correction in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-05-28 $2,255,000
10297335 Tracking address ranges for computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-05-21 $2,520,000
9318171 Dual asynchronous and synchronous memory system Gary A. Van Huben, Patrick J. Meaney, Scot H. Rider, James C. Gregerson, Eric E. Retter +4 more 2016-04-19 $3,648,000
9250666 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Gregory S. Still, Malcolm S. Allen-Ware +3 more 2016-02-02 $1,325,000
9142272 Dual asynchronous and synchronous memory system Gary A. Van Huben, Patrick J. Meaney, Scot H. Rider, James C. Gregerson, Eric E. Retter +4 more 2015-09-22 $4,871,000
9136987 Replay suspension in a memory system Mark R. Hodges, Irving G. Baysah, Patrick J. Meaney, Glenn D. Gilda 2015-09-15 $3,796,000
6823471 Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2004-11-23 $4,043,000
6658556 Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-12-02 $4,756,000
6598118 Data processing system with HSA (hashed storage architecture) Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-07-22 $10,485,000
6516404 Data processing system having hashed architected processor facilities Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-02-04 $15,040,000
6470442 Processor assigning data to hardware partition based on selectable hash of data address Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-10-22 $16,060,000
6449691 Asymmetrical cache properties within a hashed storage subsystem Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-09-10 $13,066,000
6446165 Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-09-03 $9,688,000
6253286 Apparatus for adjusting a store instruction having memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-26 $22,108,000
6249843 Store instruction having horizontal memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-19 $38,179,000
6249911 Optimizing compiler for generating store instructions having memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-19 $38,179,000
6230242 Store instruction having vertical memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-05-08 $26,391,000