JD

John S. Dodson

IBM: 24 patents #4,429 of 70,183Top 7%
Overall (All Time): #170,787 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12118236 Dynamically allocating memory controller resources for extended prefetching Eric E. Retter, Lilith Hale, Brad W. Michael 2024-10-15
11017875 Tracking address ranges for computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2021-05-25
10971246 Performing error correction in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2021-04-06
10649511 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd J. Rosedahl +3 more 2020-05-12
10353669 Managing entries in a mark table of computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-07-16
10338999 Confirming memory marks indicating an error in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-07-02
10317964 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Scot H. Rider, Todd J. Rosedahl +3 more 2019-06-11
10304560 Performing error correction in computer memory Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-05-28
10297335 Tracking address ranges for computer memory errors Marc A. Gollub, Warren E. Maule, Brad W. Michael 2019-05-21
9318171 Dual asynchronous and synchronous memory system Gary A. Van Huben, Patrick J. Meaney, Scot H. Rider, James C. Gregerson, Eric E. Retter +4 more 2016-04-19
9250666 Scalable data collection for system management Irving G. Baysah, Karthick Rajamani, Eric E. Retter, Gregory S. Still, Malcolm S. Allen-Ware +3 more 2016-02-02
9142272 Dual asynchronous and synchronous memory system Gary A. Van Huben, Patrick J. Meaney, Scot H. Rider, James C. Gregerson, Eric E. Retter +4 more 2015-09-22
9136987 Replay suspension in a memory system Mark R. Hodges, Irving G. Baysah, Patrick J. Meaney, Glenn D. Gilda 2015-09-15
6823471 Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2004-11-23
6658556 Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-12-02
6598118 Data processing system with HSA (hashed storage architecture) Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-07-22
6516404 Data processing system having hashed architected processor facilities Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2003-02-04
6470442 Processor assigning data to hardware partition based on selectable hash of data address Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-10-22
6449691 Asymmetrical cache properties within a hashed storage subsystem Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-09-10
6446165 Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, Jerry Don Lewis 2002-09-03
6253286 Apparatus for adjusting a store instruction having memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-26
6249843 Store instruction having horizontal memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-19
6249911 Optimizing compiler for generating store instructions having memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-06-19
6230242 Store instruction having vertical memory hierarchy control bits Ravi Kumar Arimilli, Guy L. Guthrie 2001-05-08