Issued Patents All Time
Showing 1–25 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8255635 | Claiming coherency ownership of a partial cache line of data | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Warren E. Maule | 2012-08-28 |
| 8117401 | Interconnect operation indicating acceptability of partial data delivery | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Warren E. Maule | 2012-02-14 |
| 8108619 | Cache management for partial cache line operations | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Warren E. Maule | 2012-01-31 |
| 8077602 | Performing dynamic request routing based on broadcast queue depths | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner | 2011-12-13 |
| 8024527 | Partial cache line accesses based on memory access patterns | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Warren E. Maule | 2011-09-20 |
| 7958309 | Dynamic selection of a memory access size | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Warren E. Maule | 2011-06-07 |
| 7921316 | Cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner | 2011-04-05 |
| 7827428 | System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner | 2010-11-02 |
| 7779148 | Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Bernard C. Drerup, Jody B. Joyner | 2010-08-17 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads | Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner | 2009-04-28 |
| 7308558 | Multiprocessor data processing system having scalable data interconnect and data routing mechanism | Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner | 2007-12-11 |
| 7302616 | Method and apparatus for performing bus tracing with scalable bandwidth in a data processing system having a distributed memory | John Steven Dodson, Gary Alan Morrison | 2007-11-27 |
| 7213169 | Method and apparatus for performing imprecise bus tracing in a data processing system having a distributed memory | John Steven Dodson, Michael Stephen Floyd, Gary Alan Morrison | 2007-05-01 |
| 7007128 | Multiprocessor data processing system having a data routing mechanism regulated through control communication | Ravi Kumar Arimilli, Vicente Enrique Chung, Jody B. Joyner | 2006-02-28 |
| 6910062 | Method and apparatus for transmitting packets within a symmetric multiprocessor system | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2005-06-21 |
| 6865695 | Robust system bus recovery | Jody B. Joyner, Ravi Kumar Arimilli, Vicente Enrique Chung | 2005-03-08 |
| 6848003 | Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2005-01-25 |
| 6823471 | Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2004-11-23 |
| 6801984 | Imprecise snooping based invalidation mechanism | Ravi Kumar Arimilli, John Steven Dodson, Guy L. Guthrie | 2004-10-05 |
| 6701416 | Cache coherency protocol with tagged intervention of modified values | Ravi Kumar Arimilli, John Steven Dodson | 2004-03-02 |
| 6671712 | Multi-node data processing system having a non-hierarchical interconnect architecture | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie, Jody B. Joyner | 2003-12-30 |
| 6662216 | Fixed bus tags for SMP buses | Ravi Kumar Arimilli, John Steven Dodson | 2003-12-09 |
| 6658536 | Cache-coherency protocol with recently read state for extending cache horizontally | Ravi Kumar Arimilli, John Steven Dodson, John Michael Kaiser | 2003-12-02 |
| 6658556 | Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2003-12-02 |
| 6598118 | Data processing system with HSA (hashed storage architecture) | Ravi Kumar Arimilli, Leo James Clark, John S. Dodson, Guy L. Guthrie | 2003-07-22 |