Issued Patents All Time
Showing 1–25 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11341060 | Multifunction communication interface supporting memory sharing among data processing systems | Michael S. Siegel, William J. Starke, Jeffrey A. Stuecheli, Kenneth M. Valk, James Francis Mikos +1 more | 2022-05-24 |
| 11113204 | Translation invalidation in a translation cache serving an accelerator | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk +1 more | 2021-09-07 |
| 11030110 | Integrated circuit and data processing system supporting address aliasing in an accelerator | Michael S. Siegel, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, Derek E. Williams +2 more | 2021-06-08 |
| 10846235 | Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator | Bartholomew Blaner, Michael S. Siegel, Jeffrey A. Stuecheli, William J. Starke, Kenneth M. Valk +1 more | 2020-11-24 |
| 10831593 | Live partition mobility enabled hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2020-11-10 |
| 10761995 | Integrated circuit and data processing system having a configurable cache directory for an accelerator | Bartholomew Blaner, Jeffrey A. Stuecheli, Michael S. Siegel, William J. Starke, Curtis C. Wollbrink +2 more | 2020-09-01 |
| 10585744 | Managed hardware accelerator address translation fault resolution utilizing a credit | Richard Louis Arndt, Bartholomew Blaner | 2020-03-10 |
| 10572337 | Live partition mobility enabled hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2020-02-25 |
| 10545816 | Managed hardware accelerator address translation fault resolution utilizing a credit | Richard Louis Arndt, Bartholomew Blaner | 2020-01-28 |
| 10528418 | Hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2020-01-07 |
| 10394711 | Managing lowest point of coherency (LPC) memory using a service layer adapter | Etai Adar, Yiftach Benjamini, Bartholomew Blaner, William J. Starke, Jeffrey A. Stuecheli | 2019-08-27 |
| 10346164 | Memory move instruction sequence targeting an accelerator switchboard | Bartholomew Blaner, William J. Starke, Randal C. Swanberg, Scott M. Willenborg | 2019-07-09 |
| 10289479 | Hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2019-05-14 |
| 10235215 | Memory lock mechanism for a multiprocessor system | Ravi Kumar Arimilli, Guy L. Guthrie, William J. Starke | 2019-03-19 |
| 10216568 | Live partition mobility enabled hardware accelerator address translation fault resolution | Richard Louis Arndt, Bartholomew Blaner | 2019-02-26 |
| 10216653 | Pre-transmission data reordering for a serial interface | Yiftach Benjamini, Bartholomew Blaner, Daniel M. Dreps, John D. Irish, David J. Krolak +6 more | 2019-02-26 |
| 10169247 | Direct memory access between an accelerator and a processor using a coherency adapter | Etai Adar, Yiftach Benjamini | 2019-01-01 |
| 10126952 | Memory move instruction sequence targeting a memory-mapped device | Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams | 2018-11-13 |
| 9996298 | Memory move instruction sequence enabling software control | Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams | 2018-06-12 |
| 9892061 | Direct memory access between an accelerator and a processor using a coherency adapter | Etai Adar, Yiftach Benjamini | 2018-02-13 |
| 9778933 | Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread | Bernard C. Drerup, Guy L. Guthrie, John D. Irish, William J. Starke, Jeffrey A. Stuecheli | 2017-10-03 |
| 9766890 | Non-serialized push instruction for pushing a message payload from a sending thread to a receiving thread | Bernard C. Drerup, Guy L. Guthrie, John D. Irish, William J. Starke, Jeffrey A. Stuecheli | 2017-09-19 |
| 9715470 | Direct memory access between an accelerator and a processor using a coherency adapter | Etai Adar, Yiftach Benjamini | 2017-07-25 |
| 9684551 | Addressing for inter-thread push communication | John D. Irish, William J. Starke, Randal C. Swanberg | 2017-06-20 |
| 9678812 | Addressing for inter-thread push communication | John D. Irish, William J. Starke, Randal C. Swanberg | 2017-06-13 |