Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394711 | Managing lowest point of coherency (LPC) memory using a service layer adapter | Lakshminarayana B. Arimilli, Yiftach Benjamini, Bartholomew Blaner, William J. Starke, Jeffrey A. Stuecheli | 2019-08-27 |
| 10296253 | Coordination of spare lane usage between link partners | Yiftach Benjamini, Pavel Granovsky | 2019-05-21 |
| 10169247 | Direct memory access between an accelerator and a processor using a coherency adapter | Lakshminarayana B. Arimilli, Yiftach Benjamini | 2019-01-01 |
| 9892061 | Direct memory access between an accelerator and a processor using a coherency adapter | Lakshminarayana B. Arimilli, Yiftach Benjamini | 2018-02-13 |
| 9715470 | Direct memory access between an accelerator and a processor using a coherency adapter | Lakshminarayana B. Arimilli, Yiftach Benjamini | 2017-07-25 |
| 9354990 | Coordination of spare lane usage between link partners | Yiftach Benjamini, Pavel Granovsky | 2016-05-31 |
| 9086965 | PCI express error handling and recovery action controls | Ilya Granovsky | 2015-07-21 |
| 9032102 | Decode data for fast PCI express multi-function device address decode | Ilya Granovsky | 2015-05-12 |
| 8601193 | Performance monitor design for instruction profiling using shared counters | Srinivasan Ramani, Eric F. Robinson, Thuong Quang Truong | 2013-12-03 |
| 8589922 | Performance monitor design for counting events generated by thread groups | Srinivasan Ramani, Eric F. Robinson, Thuong Quang Truong | 2013-11-19 |
| 8489787 | Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors | Russell D. Hoover, Srinivasan Ramani, Eric F. Robinson, Thuong Quang Truong | 2013-07-16 |
| 8417851 | Polling of a target register within a peripheral device | Eric F. Robinson, Yossi Shapira | 2013-04-09 |
| 8249177 | Detection of frame marker quality | Michael Bar-Joshua, David R. Stauffer | 2012-08-21 |
| 8024597 | Signal phase verification for systems incorporating two synchronous clock domains | Ilya Granovsky, Efrat Greenberg, Itay Poleg | 2011-09-20 |
| 7827325 | Device, system, and method of speculative packet transmission | Ilya Granovsky, Zorik Machulsky, Paul J. Mattos | 2010-11-02 |
| 7747803 | Device, system, and method of handling delayed transactions | Michael Bar-Joshua, Atar Peyser, Shaul Yohai Yifrach | 2010-06-29 |
| 7734854 | Device, system, and method of handling transactions | Michael Bar-Joshua, Ilya Granovsky, Shaul Yohai Yifrach | 2010-06-08 |
| 7562168 | Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same | Shaul Yohai Yifrach, Ilya Gransovky, Giora Biran | 2009-07-14 |
| 6611211 | Data mask coding | Dan Ramon, Gil Walzer | 2003-08-26 |
| 6021483 | PCI-to-PCI bridges with a timer register for storing a delayed transaction latency | Ophir Nadir, Yehuda Peled | 2000-02-01 |