Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12218840 | Flexible scheme for adding rules to a NIC pipeline | Manasi Deval, Elazar COHEN, Parthasarathy Sarangam | 2025-02-04 |
| 11347667 | Bus controller and related methods | Tomer Rafael Ben-Chen, Sharon Graif | 2022-05-31 |
| 11287842 | Time synchronization for clocks separated by a communication link | Yiftach Benjamini, Amit Gil | 2022-03-29 |
| 10963035 | Low power PCIe | Lalan Jee Mishra, James Lionel Panian, Richard Dominic Wietfeldt, Mohit Kishore Prasad, Amit Gil | 2021-03-30 |
| 10922252 | Extended message signaled interrupts (MSI) message data | Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel | 2021-02-16 |
| 10795400 | Time synchronization for clocks separated by a communication link | Yiftach Benjamini, Amit Gil | 2020-10-06 |
| 10645200 | Alternate acknowledgment (ACK) signals in a coalescing transmission control protocol/internet protocol (TCP/IP) system | Amit Gil | 2020-05-05 |
| 10310585 | Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems | Amit Gil, James Lionel Panian, Ofer Rosenberg, Richard Dominic Wietfeldt | 2019-06-04 |
| 10157153 | Inline cryptographic engine (ICE) for peripheral component interconnect express (PCIe) systems | Assaf Shacham, Eyal Skulsky | 2018-12-18 |
| 10089275 | Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system | Ofer Rosenberg, Amit Gil, James Lionel Panian, Piyush Patel | 2018-10-02 |
| 10042777 | Hardware-based translation lookaside buffer (TLB) invalidation | Assaf Shacham, Thomas Zeng | 2018-08-07 |
| 9998573 | Hardware-based packet processing circuitry | Tomer Rafael Ben-Chen, Amit Gil, Dan Gilboa Waizman, Deepak Jindal, Ayala Miller | 2018-06-12 |
| 8949530 | Dynamic index selection in a hardware cache | MVV Anil Krishna | 2015-02-03 |
| 7904865 | Placement driven routing | Michael Bar-Joshua, Itamar Tsachi, Boaz Yeger | 2011-03-08 |
| 7747803 | Device, system, and method of handling delayed transactions | Etai Adar, Michael Bar-Joshua, Atar Peyser | 2010-06-29 |
| 7734854 | Device, system, and method of handling transactions | Etai Adar, Michael Bar-Joshua, Ilya Granovsky | 2010-06-08 |
| 7562168 | Method of optimizing buffer usage of virtual channels of a physical communication link and apparatuses for performing the same | Ilya Gransovky, Etai Adar, Giora Biran | 2009-07-14 |
| 7500062 | Fast path memory read request processing in a multi-level memory architecture | Bruce Beukema, Michael Bar-Joshua, Alexander Mesh | 2009-03-03 |
| 7496108 | Method for dynamic management of TCP reassembly buffers | Giora Biran, Mark Epshtein, Vadim Makhervaks, Alexander Mesh, Tal Sostheim | 2009-02-24 |