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High speed memory interface |
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2017-12-26 |
| 8249177 |
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Etai Adar, Michael Bar-Joshua |
2012-08-21 |
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Automated simulation testbench generation for serializer/deserializer datapath systems |
Francis A. Kampf, Jeanne Trinko-Mechler |
2012-03-13 |
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Ming-i Mark Lin |
2011-11-01 |
| 7444258 |
Automated simulation testbench generation for serializer/deserializer datapath systems |
Francis A. Kampf, Jeanne Trinko-Mechler |
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Jeanne Trinko-Mechler |
2007-10-30 |
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Sheehan D. Lake |
2007-07-10 |
| 7191383 |
System and method for optimizing iterative circuit for cyclic redundancy check (CRC) calculation |
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| 6993671 |
High speed clock divider with synchronous phase start-up over physically distributed space |
Douglas C. Pricer |
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| 5954824 |
Test mode matrix circuit for an embedded microprocessor core |
Cory Ansel Cherichetti, Peter Stewart Colyer |
1999-09-21 |
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Test mode matrix circuit for an embedded microprocessor core |
Cory Ansel Cherichetti, Peter Stewart Colyer |
1998-03-03 |
| 5671443 |
Direct memory access acceleration device for use in a data processing system |
Rebecca Stempski McMahon |
1997-09-23 |
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FDDI network test adapter history store circuit (HSC) |
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| 5363379 |
FDDI network test adaptor error injection circuit |
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