Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8015358 | System bus structure for large L2 cache array topology with different latency domains | Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2011-09-06 |
| 7793048 | System bus structure for large L2 cache array topology with different latency domains | Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2010-09-07 |
| 7627738 | Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node | Benjiman L. Goodman, Praveen S. Reddy, William J. Starke | 2009-12-01 |
| 7526631 | Data processing system with backplane and processor books configurable to support both technical and commercial workloads | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2009-04-28 |
| 7469318 | System bus structure for large L2 cache array topology with different latency domains | Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli | 2008-12-23 |
| 7380102 | Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response | Benjiman L. Goodman, Praveen S. Reddy, William J. Starke | 2008-05-27 |
| 7308536 | System bus read data transfers with data ordering control bits | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2007-12-11 |
| 7308558 | Multiprocessor data processing system having scalable data interconnect and data routing mechanism | Ravi Kumar Arimilli, Jerry Don Lewis, Jody B. Joyner | 2007-12-11 |
| 7007128 | Multiprocessor data processing system having a data routing mechanism regulated through control communication | Ravi Kumar Arimilli, Jerry Don Lewis, Jody B. Joyner | 2006-02-28 |
| 6874063 | System bus read data transfers with data ordering control bits | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2005-03-29 |
| 6865695 | Robust system bus recovery | Jody B. Joyner, Ravi Kumar Arimilli, Jerry Don Lewis | 2005-03-08 |
| 6581116 | Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system | Ravi Kumar Arimilli, Warren E. Maule | 2003-06-17 |
| 6535957 | System bus read data transfers with bus utilization based data ordering | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2003-03-18 |
| 6487679 | Error recovery mechanism for a high-performance interconnect | Ravi Kumar Arimilli, Warren E. Maule | 2002-11-26 |
| 6360297 | System bus read address operations with data ordering preference hint bits for vertical caches | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2002-03-19 |
| 6349360 | System bus read address operations with data ordering preference hint bits | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner | 2002-02-19 |