Issued Patents All Time
Showing 25 most recent of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353330 | Preemption techniques for memory-backed registers | Yoong Chert Foo, Karl D. Mann, Terence M. Potter, Frank W. Liljeros, Jeffrey T. Brady | 2025-07-08 |
| 12190151 | Multi-stage thread scheduling | Anjana Rajendran, Sheenam Jayaswal, Terence M. Potter, Yoong Chert Foo | 2025-01-07 |
| 12182037 | Cache control to preserve register data | Jonathan Redshaw, Winnie W. Yeung, David K. Li, Zelin Zhang, Yoong Chert Foo | 2024-12-31 |
| 12164927 | Thread channel deactivation based on instruction cache misses | Justin Friesenhahn | 2024-12-10 |
| 11954492 | Fence enforcement techniques based on stall characteristics | Dzung Q. Vu, Robert D. Kenney | 2024-04-09 |
| 11947462 | Cache footprint management | Yoong Chert Foo, Terence M. Potter, Donald R. DeSota, Aroun Demeure, Cheng Li +1 more | 2024-04-02 |
| 11714759 | Private memory management using utility thread | Terence M. Potter, Anjana Rajendran, Mark I. Luffel, William V. Miller | 2023-08-01 |
| 11360780 | Instruction-level context switch in SIMD processor | Terence M. Potter, Anjana Rajendran, Jeffrey T. Brady, Brian K. Reynolds, Jeffrey A. Lohman | 2022-06-14 |
| 11204774 | Thread-group-scoped gate instruction | Anjana Rajendran, Jeffrey A. Lohman, Terence M. Potter | 2021-12-21 |
| 10902545 | GPU task scheduling | Robert D. Kenney, Terence M. Potter | 2021-01-26 |
| 10769746 | Data alignment and formatting for graphics processing unit | Liang Xia, Robert D. Kenney, Terence M. Potter | 2020-09-08 |
| 10503546 | GPU resource priorities based on hardware utilization | Tatsuya Iwamoto, Kutty Banerjee, Terence M. Potter | 2019-12-10 |
| 10270434 | Power saving with dynamic pulse insertion | James Wang, Liang-Kai Wang, Robert D. Kenney | 2019-04-23 |
| 9811875 | Texture state cache | Adam T. Moerschell, James S. Blomgren | 2017-11-07 |
| 9632954 | Memory queue handling techniques for reducing impact of high-latency memory operations | Mark A. Brittain, John Steven Dodson, Stephen J. Powell, Eric E. Retter, Jeffrey A. Stuecheli | 2017-04-25 |
| 9519944 | Pipeline dependency resolution | Robert D. Kenney, Gregory D. Roberts | 2016-12-13 |
| 9477550 | ECC bypass using low latency CE correction with retry select signal | Luis A. Lastras-Montano, Eric E. Retter, Kenneth L. Wright | 2016-10-25 |
| 9471410 | Transient condition management utilizing a posted error detection processing protocol | John Steven Dodson, Guy L. Guthrie, Eric E. Retter, William J. Starke, Jeffrey A. Stuecheli | 2016-10-18 |
| 9436548 | ECC bypass using low latency CE correction with retry select signal | Luis A. Lastras-Montano, Eric E. Retter, Kenneth L. Wright | 2016-09-06 |
| 9384146 | Dynamic reservations in a unified request queue | Harrison M. McCreary, Eric E. Retter, Steven L. Roberts, Jeffrey A. Stuecheli | 2016-07-05 |
| 9384136 | Modification of prefetch depth based on high latency event | John Steven Dodson, Miles Robert Dooley, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-07-05 |
| 9378144 | Modification of prefetch depth based on high latency event | John Steven Dodson, Miles Robert Dooley, Jody B. Joyner, Stephen J. Powell, Eric E. Retter +1 more | 2016-06-28 |
| 9361240 | Dynamic reservations in a unified request queue | Harrison M. McCreary, Eric E. Retter, Steven L. Roberts, Jeffrey A. Stuecheli | 2016-06-07 |
| 9355035 | Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed threshold | Jody B. Joyner, Stephen J. Powell, William J. Starke, Jeffrey A. Stuecheli | 2016-05-31 |
| 9231618 | Early data tag to allow data CRC bypass via a speculative memory data return protocol | Harrison M. McCreary, Stephen J. Powell, William J. Starke, Jeffrey A. Stuecheli | 2016-01-05 |