Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405803 | Superscalar execution using pipelines that support different precisions | Christopher A. Burns | 2025-09-02 |
| 12008377 | SIMD operand permutation with selection from among multiple registers | Christopher A. Burns, Robert D. Kenney, Terence M. Potter | 2024-06-11 |
| 11836459 | Floating-point division circuitry with subnormal support | Ian R. Ollmann, Anthony Y. Tai | 2023-12-05 |
| 11727530 | Instruction storage | Andrew M. Havlir, Dzung Q. Vu | 2023-08-15 |
| 11645084 | SIMD operand permutation with selection from among multiple registers | Christopher A. Burns, Robert D. Kenney, Terence M. Potter | 2023-05-09 |
| 11439871 | System and method for rehabilitation | Yan Liu, Po-Jui Huang, Chung-Hsien Wu, Jian Chen | 2022-09-13 |
| 11372621 | Circuitry for floating-point power function | Anthony Y. Tai, Ian R. Ollmann, Anand Poovekurussi | 2022-06-28 |
| 11294672 | Routing circuitry for permutation of single-instruction multiple-data operands | Robert D. Kenney, Terence M. Potter | 2022-04-05 |
| 11256518 | Datapath circuitry for math operations using SIMD pipelines | Robert D. Kenney, Terence M. Potter, Vinod Reddy Nalamalapu, Sivayya Ayinala | 2022-02-22 |
| 11210761 | Circuitry to determine set of priority candidates | Vinod Reddy Nalamalapu | 2021-12-28 |
| 11126439 | SIMD operand permutation with selection from among multiple registers | Christopher A. Burns, Robert D. Kenney, Terence M. Potter | 2021-09-21 |
| 11023997 | Instruction storage | Andrew M. Havlir, Dzung Q. Vu | 2021-06-01 |
| 10503473 | Floating-point division alternative techniques | Anthony Y. Tai, Luc R. Semeria, Xiao-Long Wu | 2019-12-10 |
| 10481869 | Multi-path fused multiply-add with power control | Ting Yu, Yu P. Sun | 2019-11-19 |
| 10387119 | Processing circuitry for encoded fields of related threads | Terence M. Potter, Brian K. Reynolds, Justin Friesenhahn | 2019-08-20 |
| 10282169 | Floating-point multiply-add with down-conversion | Terence M. Potter, Andrew M. Havlir, Yu Sun, Nicolas X. Pena, Xiao-Long Wu +1 more | 2019-05-07 |
| 10270434 | Power saving with dynamic pulse insertion | James Wang, Benjiman L. Goodman, Robert D. Kenney | 2019-04-23 |
| 10223582 | Gait recognition method based on deep learning | Tieniu Tan, Yongzhen Huang, Zifeng Wu | 2019-03-05 |
| 10114650 | Pessimistic dependency handling based on storage regions | Robert D. Kenney | 2018-10-30 |
| 10096121 | Human-shape image segmentation method | Tieniu Tan, Yongzhen Huang, Zifeng Wu | 2018-10-09 |
| 10089077 | Parallel processing circuitry for encoded fields of related threads | Terence M. Potter, Brian K. Reynolds, Justin Friesenhahn | 2018-10-02 |
| 9846579 | Unified integer and floating-point compare circuitry | Terence M. Potter, Andrew M. Havlir | 2017-12-19 |
| 9841948 | Microarchitecture for floating point fused multiply-add with exponent scaling | — | 2017-12-12 |
| 9785567 | Operand cache control techniques | Andrew M. Havlir, Terence M. Potter | 2017-10-10 |
| 9727944 | GPU instruction storage | Andrew M. Havlir, Dzung Q. Vu | 2017-08-08 |