Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12384562 | System and method for capturing space target | Jinsheng Guo, Fan Wu, Shi Qiu, Cheng Wei, Hongxu WANG | 2025-08-12 |
| 12389673 | Semiconductor structure and method of forming semiconductor structure | Shiliang JI, Haiyang Zhang | 2025-08-12 |
| 11881480 | Semiconductor structure and method of forming semiconductor structure | Shiliang JI, Haiyang Zhang | 2024-01-23 |
| 11439871 | System and method for rehabilitation | Yan Liu, Po-Jui Huang, Liang-Kai Wang, Chung-Hsien Wu | 2022-09-13 |
| 11211475 | Semiconductor device and formation method thereof | Haiyang Zhang, Bo SU | 2021-12-28 |
| 9466522 | Method for fabricating semiconductor structure | Ta-Chien Chiu | 2016-10-11 |
| 8269912 | Display device for preventing electromagnetic interference | Huang-Pin Lin, Chien-Cheng Lin, Kuan-Yu Chen, Yi-An Chien, Hung-Tsai Weng | 2012-09-18 |
| 8179683 | Display device | Huang-Pin Lin, Chien-Cheng Lin, Kuan-Yu Chen, Yi-An Chien, Hung-Tsai Weng | 2012-05-15 |
| 7615806 | Method for forming a semiconductor structure and structure thereof | Voon-Yew Thean, Bich-Yen Nguyen, Mariam Sadaka, Da Zhang | 2009-11-10 |
| 7575975 | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer | Voon-Yew Thean, Bich-Yen Nguyen, Mariam Sadaka, Da Zhang | 2009-08-18 |
| 7288447 | Semiconductor device having trench isolation for differential stress and method therefor | Thien T. Nguyen, Michael D. Turner, James E. Vasek | 2007-10-30 |
| 7276406 | Transistor structure with dual trench for optimized stress effect and method therefor | Michael D. Turner, James E. Vasek | 2007-10-02 |
| 7161199 | Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof | Michael A. Mendicino, Vance H. Adams, Choh Fei Yeap, Venkat R. Kolagunta | 2007-01-09 |
| 7125805 | Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing | Rode R. Mora, Marc Rossow, Yasuhito Shiho | 2006-10-24 |
| 7074713 | Plasma enhanced nitride layer | Stanley M. Filipiak, Yongjoo Jeon, Tab A. Stephens | 2006-07-11 |
| 7064396 | Integrated circuit with multiple spacer insulating region widths | Vance H. Adams, Choh Fei Yeap | 2006-06-20 |
| 6864135 | Semiconductor fabrication process using transistor spacers of differing widths | Paul A. Grudowski, Choh Fei Yeap | 2005-03-08 |
| 6503814 | Method for forming trench isolation | Choh Fei Yeap, Franklin D. Nkansah | 2003-01-07 |
| 6049114 | Semiconductor device having a metal containing layer overlying a gate dielectric | Bikas Maiti, Jon J. Candelaria | 2000-04-11 |