Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10884481 | Apparatus and method for improving power savings by accelerating device suspend and resume operations | Shaun Pinney, Hiroyasu Ito | 2021-01-05 |
| 10459508 | Low frequency power management bus | Sarma Sista | 2019-10-29 |
| 9385416 | Three dimensional antenna dome array | Gururaj Govindasamy, Hogan Lew, Prakash Guda, Stephen Strong | 2016-07-05 |
| 7996698 | System and method for enabling functionality based on measured power | Giridhara Gopalan | 2011-08-09 |
| 7288447 | Semiconductor device having trench isolation for differential stress and method therefor | Jian Chen, Michael D. Turner, James E. Vasek | 2007-10-30 |
| 7091071 | Semiconductor fabrication process including recessed source/drain regions in an SOI wafer | Voon-Yew Thean, Brian J. Goolsby, Bich-Yen Nguyen, Tab A. Stephens | 2006-08-15 |
| 6554004 | Method for removing etch residue resulting from a process for forming a via | Valentin Medina, Jr., Douglas J. Dopp | 2003-04-29 |
| 6322660 | Apparatus and method for remote endpoint detection | Michael Patrick McFee, Stephanie Annette Grahn | 2001-11-27 |
| 6281132 | Device and method for etching nitride spacers formed upon an integrated circuit gate conductor | Mark I. Gardner, Charles E. May | 2001-08-28 |
| 6248252 | Method of fabricating sub-micron metal lines | Mark I. Gardner | 2001-06-19 |
| 6242317 | High quality isolation structure formation | Mark I. Gardner, Charles E. May | 2001-06-05 |
| 6207544 | Method of fabricating ultra thin nitride spacers and device incorporating same | Mark I. Gardner, Charles E. May | 2001-03-27 |
| 6180465 | Method of making high performance MOSFET with channel scaling mask feature | Mark I. Gardner | 2001-01-30 |
| 6162692 | Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor | Mark I. Gardner, Derrick J. Wristers | 2000-12-19 |
| 6150222 | Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions | Mark I. Gardner, Charles E. May | 2000-11-21 |
| 6114251 | Method of fabrication for ultra thin nitride liner in silicon trench isolation | Mark I. Gardner, Frederick N. Hause | 2000-09-05 |
| 6080676 | Device and method for etching spacers formed upon an integrated circuit gate conductor | Mark I. Gardner, Charles E. May | 2000-06-27 |
| 6074919 | Method of forming an ultrathin gate dielectric | Mark I. Gardner | 2000-06-13 |
| 6001171 | ST-cut and AT-cut oriented seed bodies for quartz crystal synthesis and method for making the same | Joseph F. Balascio, David J. Weary, Theodore E. Lind | 1999-12-14 |
| 5814186 | SOG etchant gas and method for using same | — | 1998-09-29 |
| 5714005 | ST-cut and AT-cut oriented seed bodies for quartz crystal synthesis and method for making the same | Joseph F. Balascio, David J. Weary, Theodore E. Lind | 1998-02-03 |