Issued Patents All Time
Showing 1–25 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11585775 | Method and system for integrity testing of sachets | Hari Krishna Salila Vijayalal Mohan, Suryakanta Nayak | 2023-02-21 |
| 10340139 | Methods and mask structures for substantially defect-free epitaxial growth | Benjamin Vincent, Liesbeth Witters | 2019-07-02 |
| 10309925 | FET biosensor | Nadine Collaert | 2019-06-04 |
| 10211312 | Ferroelectric memory device and fabrication method thereof | Jan Van Houdt | 2019-02-19 |
| 9476143 | Methods using mask structures for substantially defect-free epitaxial growth | Benjamin Vincent, Liesbeth Witters | 2016-10-25 |
| 9368498 | FinFET device with dual-strained channels and method for manufacturing thereof | Geert Eneman, Benjamin Vincent | 2016-06-14 |
| 9171904 | FinFET device with dual-strained channels and method for manufacturing thereof | Geert Eneman, Benjamin Vincent | 2015-10-27 |
| 8623714 | Spacer protection and electrical connection for array device | Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Ava Wan +2 more | 2014-01-07 |
| 8587039 | Method of forming a semiconductor device featuring a gate stressor and semiconductor device | Brian A. Winstead, Konstantin V. Loiko | 2013-11-19 |
| 8563394 | Integrated circuit structure having substantially planar N-P step height and methods of forming | Weipeng Li, Deleep R. Nair, Jae-Eun Park, Young Way Teh | 2013-10-22 |
| 8106462 | Balancing NFET and PFET performance using straining layers | Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony +8 more | 2012-01-31 |
| 8039341 | Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit | Bich-Yen Nguyen, Da Zhang | 2011-10-18 |
| 8003454 | CMOS process with optimized PMOS and NMOS transistor devices | Da Zhang, Srikanth B. Samavedam, Xiangdong Chen | 2011-08-23 |
| 7960243 | Method of forming a semiconductor device featuring a gate stressor and semiconductor device | Brian A. Winstead, Konstantin V. Loiko | 2011-06-14 |
| 7911002 | Semiconductor device with selectively modulated gate work function | Marc Rossow, Gregory S. Spencer, Tab A. Stephens, Dina H. Triyoso, Victor H. Vartanian | 2011-03-22 |
| 7883953 | Method for transistor fabrication with optimized performance | Da Zhang, Christopher V. Baiocco, Jie Chen, Weipeng Li, Young Way Teh +1 more | 2011-02-08 |
| 7867839 | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors | Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein | 2011-01-11 |
| 7821067 | Electronic devices including a semiconductor layer | Brian J. Goolsby, Linda B. McCormick, Bich-Yen Nguyen, Colita M. Parker, Mariam Sadaka +3 more | 2010-10-26 |
| 7811382 | Method for forming a semiconductor structure having a strained silicon layer | Mariam Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Ted R. White | 2010-10-12 |
| 7803670 | Twisted dual-substrate orientation (DSO) substrates | Ted R. White, Leo Mathew, Bich-Yen Nguyen, Zhonghai Shi, Mariam Sadaka | 2010-09-28 |
| 7781840 | Semiconductor device structure | Ted R. White, Alexander L. Barr, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka | 2010-08-24 |
| 7781839 | Structure and method for strained transistor directly on insulator | Bich-Yen Nguyen | 2010-08-24 |
| 7781277 | Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit | Bich-Yen Nguyen | 2010-08-24 |
| 7763510 | Method for PFET enhancement | Da Zhang | 2010-07-27 |
| 7737018 | Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer | Leo Mathew, Vishal P. Trivedi | 2010-06-15 |