Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11322465 | Metal layer patterning for minimizing mechanical stress in integrated circuit packages | Kathryn R. Holland, Marc Tarabbia, Yaoyu Pang | 2022-05-03 |
| 10586865 | Dual gate metal-oxide-semiconductor field-effect transistor | Scott Warrick, Justin Dougherty, Christian Larsen, Marc Tarabbia, Ying Ying | 2020-03-10 |
| 7927956 | Method for making a semiconductor structure using silicon germanium | Marius Orlowski, Mariam Sadaka, Ted R. White | 2011-04-19 |
| 7811382 | Method for forming a semiconductor structure having a strained silicon layer | Mariam Sadaka, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White | 2010-10-12 |
| 7781840 | Semiconductor device structure | Ted R. White, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean | 2010-08-24 |
| 7282402 | Method of making a dual strained channel semiconductor device | Mariam Sadaka, Dejan Jovanovic, Bich-Yen Nguyen, Voon-Yew Thean, Shawn George Thomas +1 more | 2007-10-16 |
| 7241647 | Graded semiconductor layer | Mariam Sadaka, Shawn George Thomas, Ted R. White, Chun-Li Liu, Bich-Yen Nguyen +1 more | 2007-07-10 |
| 7226833 | Semiconductor device structure and method therefor | Ted R. White, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean | 2007-06-05 |
| 7208357 | Template layer formation | Mariam Sadaka, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White | 2007-04-24 |
| 7205210 | Semiconductor structure having strained semiconductor and method therefor | Dejan Jovanovic, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean, Ted R. White | 2007-04-17 |
| 7163903 | Method for making a semiconductor structure using silicon germanium | Marius Orlowski, Mariam Sadaka, Ted R. White | 2007-01-16 |
| 7160769 | Channel orientation to enhance transistor performance | Ted R. White, Dejan Jovanovic, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean | 2007-01-09 |
| 7067868 | Double gate device having a heterojunction source/drain and strained channel | Voon-Yew Thean, Mariam Sadaka, Ted R. White, Venkat R. Kolagunta, Bich-Yen Nguyen +2 more | 2006-06-27 |
| 7056778 | Semiconductor layer formation | Chun-Li Liu, Mariam Sadaka, Bich-Yen Nguyen, Voon-Yew Thean, Shawn George Thomas +2 more | 2006-06-06 |
| 7045432 | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) | Marius Orlowski, Olubunmi O. Adetutu | 2006-05-16 |
| 7037795 | Low RC product transistors in SOI semiconductor process | Olubunmi O. Adetutu, Bich-Yen Nguyen, Marius Orlowski, Mariam Sadaka, Voon-Yew Thean +1 more | 2006-05-02 |
| 7029980 | Method of manufacturing SOI template layer | Chun-Li Liu, Marius Orlowski, Matthew W. Stoker, Philip J. Tobin, Mariam Sadaka +4 more | 2006-04-18 |
| 7018901 | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain | Voon-Yew Thean, Mariam Sadaka, Ted R. White, Venkat R. Kolagunta, Bich-Yen Nguyen +2 more | 2006-03-28 |
| 6964911 | Method for forming a semiconductor device having isolation regions | Marius Orlowski | 2005-11-15 |
| 6838322 | Method for forming a double-gated semiconductor device | Daniel T. Pham, Leo Mathew, Bich-Yen Nguyen, Anne Vandooren, Ted R. White | 2005-01-04 |
| 6831350 | Semiconductor structure with different lattice constant materials and method for forming the same | Chun-Li Liu, John M. Grant, Bich-Yen Nguyen, Marius Orlowski, Tab A. Stephens +2 more | 2004-12-14 |
| 6713381 | Method of forming semiconductor device including interconnect barrier layers | Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi O. Adetutu, Stuart E. Greer +5 more | 2004-03-30 |