Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10910471 | Device with large EPI in FinFETs and method of manufacturing | Jianwei Peng, Sang Woo Lim, Huang Liu, Jinping Liu | 2021-02-02 |
| 10529831 | Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging | Qun Gao, Haigou Huang | 2020-01-07 |
| 10396078 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Mira Park, George R. Mulfinger +1 more | 2019-08-27 |
| 10204984 | Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicide | Judson R. Holt, Timothy J. McArdle, Annie Levesque | 2019-02-12 |
| 10121706 | Semiconductor structure including two-dimensional and three-dimensional bonding materials | Rinus Tek Po Lee, Bharat Krishnan, Hui Zang | 2018-11-06 |
| 10020307 | Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same | Judson R. Holt, Christopher D. Sheraw, Timothy J. McArdle, Mira Park, George R. Mulfinger +1 more | 2018-07-10 |
| 9673295 | Contact resistance optimization via EPI growth engineering | Annie Levesque, Viorel Ontalus | 2017-06-06 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 9236477 | Graphene transistor with a sublithographic channel width | Jack O. Chu, Christos D. Dimitrakopoulos, Eric C. Harley, Judson R. Holt, Timothy J. McArdle | 2016-01-12 |
| 9190406 | Fin field effect transistors having heteroepitaxial channels | Emre Alptekin, Wing L. Lai, Ravikumar Ramachandran, Henry K. Utomo, Reinaldo Vega | 2015-11-17 |
| 8940595 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2015-01-27 |
| 8779525 | Method for growing strain-inducing materials in CMOS circuits in a gate first flow | Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel Ontalus +2 more | 2014-07-15 |
| 8618617 | Field effect transistor device | Kevin K. Chan, Abhishek Dube, Eric C. Harley, Judson R. Holt, Viorel Ontalus +3 more | 2013-12-31 |
| 8492234 | Field effect transistor device | Kevin K. Chan, Abhishek Dube, Eric C. Harley, Judson R. Holt, Viorel Ontalus +3 more | 2013-07-23 |
| 8426265 | Method for growing strain-inducing materials in CMOS circuits in a gate first flow | Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel Ontalus +2 more | 2013-04-23 |
| 8361859 | Stressed transistor with improved metastability | Thomas N. Adam, Stephen W. Bedell, Abhishek Dube, Eric C. Harley, Judson R. Holt +4 more | 2013-01-29 |
| 7932189 | Process of forming an electronic device including a layer of discontinuous storage elements | Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius Orlowski, Rajesh A. Rao | 2011-04-26 |
| 7928502 | Transistor devices with nano-crystal gate structures | Chun-Li Liu, Tushar P. Merchant, Marius Orlowski | 2011-04-19 |
| 7700438 | MOS device with nano-crystal gate structure | Chun-Li Liu, Tushar P. Merchant, Marius Orlowski | 2010-04-20 |
| 7683443 | MOS devices with multi-layer gate stack | Chun-Li Liu, Marius Orlowski | 2010-03-23 |
| 7510956 | MOS device with multi-layer gate stack | Chun-Li Liu, Marius Orlowski | 2009-03-31 |
| 7238580 | Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration | Marius Orlowski, Vance H. Adams, Chun-Li Liu | 2007-07-03 |
| 7029980 | Method of manufacturing SOI template layer | Chun-Li Liu, Marius Orlowski, Philip J. Tobin, Mariam Sadaka, Alexander L. Barr +4 more | 2006-04-18 |