Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11915983 | Structures and methods of fabricating electronic devices using separation and charge depletion techniques | Leo Mathew, Daniel Fine, Vishal P. Trivedi | 2024-02-27 |
| 11610819 | Structures and methods of fabricating electronic devices using separation and charge depletion techniques | Leo Mathew, Daniel Fine, Vishal P. Trivedi | 2023-03-21 |
| 8803217 | Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode | Ramachandran Muralidhar | 2014-08-12 |
| 8563355 | Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET | Leo Mathew, Tushar P. Merchant, Ramachandran Muralidhar | 2013-10-22 |
| 8097873 | Phase change memory structures | Ramachandran Muralidhar, Tushar P. Merchant | 2012-01-17 |
| 8080439 | Method of making a vertical phase change memory (PCM) and a PCM device | Arturo Martinez | 2011-12-20 |
| 7932189 | Process of forming an electronic device including a layer of discontinuous storage elements | Tushar P. Merchant, Chun-Li Liu, Ramachandran Muralidhar, Marius Orlowski, Matthew W. Stoker | 2011-04-26 |
| 7820491 | Light erasable memory and method therefor | Leo Mathew, Ramachandran Muralidhar, Bruce E. White | 2010-10-26 |
| 7816211 | Method of making a semiconductor device having high voltage transistors, non-volatile memory transistors, and logic transistors | Ramachandran Muralidhar | 2010-10-19 |
| 7811851 | Phase change memory structures | Ramachandran Muralidhar, Tushar P. Merchant | 2010-10-12 |
| 7811886 | Split-gate thin film storage NVM cell with reduced load-up/trap-up effects | Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Sung-Taeg Kang +2 more | 2010-10-12 |
| 7800164 | Nanocrystal non-volatile memory cell and method therefor | Ramachandran Muralidhar, Michael A. Sadd, Bruce E. White | 2010-09-21 |
| 7795091 | Method of forming a split gate memory device and apparatus | Brian A. Winstead, Spencer E. Williams | 2010-09-14 |
| 7767588 | Method for forming a deposited oxide layer | Tien Ying Luo | 2010-08-03 |
| 7719039 | Phase change memory structures including pillars | Ramachandran Muralidhar, Tushar P. Merchant | 2010-05-18 |
| 7704830 | Split gate memory cell using sidewall spacers | Tushar P. Merchant, Ramachandran Muralidhar, Lakshmanna Vishnubhotla | 2010-04-27 |
| 7642163 | Process of forming an electronic device including discontinuous storage elements within a dielectric layer | Tushar P. Merchant, Ramachandran Muralidhar, Gowrishankar L. Chindalore, David C. Sing, Jane A. Yater | 2010-01-05 |
| 7579238 | Method of forming a multi-bit nonvolatile memory device | Ramachandran Muralidhar | 2009-08-25 |
| 7563662 | Processes for forming electronic devices including non-volatile memory | Ramachandran Muralidhar | 2009-07-21 |
| 7557008 | Method of making a non-volatile memory device | Ramachandran Muralidhar | 2009-07-07 |
| 7528047 | Self-aligned split gate memory cell and method of forming | Tushar P. Merchant, Ramachandran Muralidhar, Lakshmanna Vishnubhotla | 2009-05-05 |
| 7517747 | Nanocrystal non-volatile memory cell and method therefor | Ramachandran Muralidhar, Michael A. Sadd, Bruce E. White | 2009-04-14 |
| 7479429 | Split game memory cell method | Ramachandran Muralidhar, Leo Mathew | 2009-01-20 |
| 7445984 | Method for removing nanoclusters from selected regions | Tien Ying Luo, Ramachandran Muralidhar, Robert F. Steimle, Sherry G. Straub | 2008-11-04 |
| 7432158 | Method for retaining nanocluster size and electrical characteristics during processing | Tien Ying Luo, Ramachandran Muralidhar, Robert F. Steimle, Sherry G. Straub | 2008-10-07 |