Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10026820 | Split gate device with doped region and method therefor | Weize Chen, Cheong Min Hong, Jane A. Yater | 2018-07-17 |
| 9847397 | Method of forming split gate memory with improved reliability | Cheong Min Hong, Jane A. Yater | 2017-12-19 |
| 9548314 | Method of making a non-volatile memory (NVM) with trap-up reduction | Cheong Min Hong, Juanyi Yin | 2017-01-17 |
| 9397176 | Method of forming split gate memory with improved reliability | Cheong Min Hong, Jane A. Yater | 2016-07-19 |
| 9379222 | Method of making a split gate non-volatile memory (NVM) cell | Brian A. Winstead | 2016-06-28 |
| 9343314 | Split gate nanocrystal memory integration | Brian A. Winstead | 2016-05-17 |
| 9331160 | Split-gate non-volatile memory cells having gap protection zones | Spencer E. Williams, Brian A. Winstead | 2016-05-03 |
| 9257445 | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor | Brian A. Winstead | 2016-02-09 |
| 9202930 | Memory with discrete storage elements | Brian A. Winstead, Mehul D. Shroff | 2015-12-01 |
| 9111867 | Split gate nanocrystal memory integration | Brian A. Winstead | 2015-08-18 |
| 8962416 | Split gate non-volatile memory cell | Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Jane A. Yater | 2015-02-24 |
| 8962410 | Transistors with different threshold voltages | Da Zhang, Spencer E. Williams, Brian A. Winstead | 2015-02-24 |
| 8766362 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Toni D. Van Gompel, Rode R. Mora, Michael D. Turner, Brian A. Winstead, Mark D. Hall | 2014-07-01 |
| 8587039 | Method of forming a semiconductor device featuring a gate stressor and semiconductor device | Brian A. Winstead, Voon-Yew Thean | 2013-11-19 |
| 8236638 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Toni D. Van Gompel, Rode R. Mora, Michael D. Turner, Brian A. Winstead, Mark D. Hall | 2012-08-07 |
| 8035156 | Split-gate non-volatile memory cell and method | Brian A. Winstead, Gowrishankar L. Chindalore, Horacio P. Gasquet | 2011-10-11 |
| 7985649 | Method of making a semiconductor structure useful in making a split gate non-volatile memory cell | Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Spencer E. Williams | 2011-07-26 |
| 7960243 | Method of forming a semiconductor device featuring a gate stressor and semiconductor device | Brian A. Winstead, Voon-Yew Thean | 2011-06-14 |
| 7960267 | Method for making a stressed non-volatile memory device | Brian A. Winstead, Taras A. Kirichenko | 2011-06-14 |
| 7821055 | Stressed semiconductor device and method for making | Cheong Min Hong, Sung-Taeg Kang, Taras A. Kirichenko, Brian A. Winstead | 2010-10-26 |
| 7811886 | Split-gate thin film storage NVM cell with reduced load-up/trap-up effects | Brian A. Winstead, Taras A. Kirichenko, Ramachandran Muralidhar, Rajesh A. Rao, Sung-Taeg Kang +2 more | 2010-10-12 |
| 7799650 | Method for making a transistor with a stressor | Xiangzheng Bo, Venkat R. Kolagunta | 2010-09-21 |
| 7521314 | Method for selective removal of a layer | Dharmesh Jawarani, Andrew G. Nagy | 2009-04-21 |
| 6380610 | Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect | Igor Peidous, Elgin Quek, David Yeo Yong Hock | 2002-04-30 |
| 6249035 | LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect | Igor Peidous, Quek Kiok Boone Elgin, Tan Poh Suan, Vijai Kumar Chhagan | 2001-06-19 |