Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10026820 | Split gate device with doped region and method therefor | Weize Chen, Cheong Min Hong, Konstantin V. Loiko | 2018-07-17 |
| 9847397 | Method of forming split gate memory with improved reliability | Cheong Min Hong, Konstantin V. Loiko | 2017-12-19 |
| 9685339 | Scalable split gate memory cell array | Cheong Min Hong, Sung-Taeg Kang, Ronald J. Syzdek | 2017-06-20 |
| 9397176 | Method of forming split gate memory with improved reliability | Cheong Min Hong, Konstantin V. Loiko | 2016-07-19 |
| 9397201 | Non-volatile memory (NVM) cell and a method of making | Jacob T. Williams, Cheong Min Hong, Sung-Taeg Kang, David G. Kolar | 2016-07-19 |
| 9331092 | Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays | Cheong Min Hong, Sung-Taeg Kang | 2016-05-03 |
| 9275864 | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates | Asanga H. Perera, Sung-Taeg Kang, Cheong Min Hong | 2016-03-01 |
| 9252246 | Integrated split gate non-volatile memory cell and logic device | Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang | 2016-02-02 |
| 9219167 | Non-volatile memory (NVM) cell | Jacob T. Williams, Cheong Min Hong, Sung-Taeg Kang, David G. Kolar | 2015-12-22 |
| 9129855 | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology | Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang | 2015-09-08 |
| 9082650 | Integrated split gate non-volatile memory cell and logic structure | Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min | 2015-07-14 |
| 9054208 | Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays | Cheong Min Hong, Sung-Taeg Kang | 2015-06-09 |
| 9006093 | Non-volatile memory (NVM) and high voltage transistor integration | Cheong Min Hong, Sung-Taeg Kang | 2015-04-14 |
| 8969940 | Method of gate strapping in split-gate memory cell with inlaid gate | Cheong Min Hong, Sung-Taeg Kang, Asanga H. Perera | 2015-03-03 |
| 8962416 | Split gate non-volatile memory cell | Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko | 2015-02-24 |
| 8901632 | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology | Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min | 2014-12-02 |
| 8679912 | Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor | Sung-Taeg Kang, Gowrishankar L. Chindalore, Brian A. Winstead | 2014-03-25 |
| 8431471 | Method for integrating a non-volatile memory (NVM) | Sung-Taeg Kang, Mehul D. Shroff | 2013-04-30 |
| 8372699 | Method for forming a split-gate memory cell | Sung-Taeg Kang | 2013-02-12 |
| 8329543 | Method for forming a semiconductor device having nanocrystals | Sung-Taeg Kang | 2012-12-11 |
| 8329544 | Method for forming a semiconductor device having nanocrystals | Sung-Taeg Kang | 2012-12-11 |
| 7902022 | Self-aligned in-laid split gate memory and method of making | Sung-Taeg Kang | 2011-03-08 |
| 7811886 | Split-gate thin film storage NVM cell with reduced load-up/trap-up effects | Brian A. Winstead, Taras A. Kirichenko, Konstantin V. Loiko, Ramachandran Muralidhar, Rajesh A. Rao +2 more | 2010-10-12 |
| 7642163 | Process of forming an electronic device including discontinuous storage elements within a dielectric layer | Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar, Gowrishankar L. Chindalore, David C. Sing | 2010-01-05 |
| 7471560 | Electronic device including a memory array and conductive lines | Gowrishankar L. Chindalore, Cheong Min Hong | 2008-12-30 |