Issued Patents All Time
Showing 25 most recent of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847389 | Semiconductor device including an active region and two layers having different stress characteristics | Vance H. Adams, Paul A. Grudowski | 2017-12-19 |
| 9449713 | Method for preconditioning thin film storage array for data retention | Horacio P. Gasquet | 2016-09-20 |
| 9425055 | Split gate memory cell with a layer of nanocrystals with improved erase performance | Ko-Min Chang, Craig T. Swift | 2016-08-23 |
| 9379222 | Method of making a split gate non-volatile memory (NVM) cell | Konstantin V. Loiko | 2016-06-28 |
| 9343314 | Split gate nanocrystal memory integration | Konstantin V. Loiko | 2016-05-17 |
| 9331160 | Split-gate non-volatile memory cells having gap protection zones | Konstantin V. Loiko, Spencer E. Williams | 2016-05-03 |
| 9257445 | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor | Konstantin V. Loiko | 2016-02-09 |
| 9202930 | Memory with discrete storage elements | Konstantin V. Loiko, Mehul D. Shroff | 2015-12-01 |
| 9111908 | Split-gate non-volatile memory cells having improved overlap tolerance | Ted R. White, Gowrishankar L. Chindalore | 2015-08-18 |
| 9111867 | Split gate nanocrystal memory integration | Konstantin V. Loiko | 2015-08-18 |
| 8962410 | Transistors with different threshold voltages | Da Zhang, Konstantin V. Loiko, Spencer E. Williams | 2015-02-24 |
| 8962416 | Split gate non-volatile memory cell | Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko, Jane A. Yater | 2015-02-24 |
| 8885403 | Programming a split gate bit cell | Cheong Min Hong, Ronald J. Syzdek | 2014-11-11 |
| 8884358 | Method of making a non-volatile memory (NVM) cell structure | Sung-Taeg Kang, Marc Rossow | 2014-11-11 |
| 8835295 | Split gate memory device with gap spacer | Jinmiao J. Shen, Ko-Min Chang | 2014-09-16 |
| 8766362 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Konstantin V. Loiko, Toni D. Van Gompel, Rode R. Mora, Michael D. Turner, Mark D. Hall | 2014-07-01 |
| 8724399 | Methods and systems for erase biasing of split-gate non-volatile memory cells | Sung-Taeg Kang | 2014-05-13 |
| 8679912 | Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor | Sung-Taeg Kang, Gowrishankar L. Chindalore, Jane A. Yater | 2014-03-25 |
| 8643123 | Method of making a semiconductor structure useful in making a split gate non-volatile memory cell | Cheong Min Hong | 2014-02-04 |
| 8587039 | Method of forming a semiconductor device featuring a gate stressor and semiconductor device | Konstantin V. Loiko, Voon-Yew Thean | 2013-11-19 |
| 8569858 | Semiconductor device including an active region and two layers having different stress characteristics | Vance H. Adams, Paul A. Grudowski | 2013-10-29 |
| 8390026 | Electronic device including a heterojunction region | Ted R. White | 2013-03-05 |
| 8283244 | Method for forming one transistor DRAM cell structure | James D. Burnett | 2012-10-09 |
| 8263463 | Nonvolatile split gate memory cell having oxide growth | Sung-Taeg Kang | 2012-09-11 |
| 8236638 | Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner | Konstantin V. Loiko, Toni D. Van Gompel, Rode R. Mora, Michael D. Turner, Mark D. Hall | 2012-08-07 |