Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10825512 | Memory reads of weight values | Frank K. Baker, Jr., Thomas Jew | 2020-11-03 |
| 9837161 | Split-gate memory having sector retirement with reduced current and method therefor | Gilles J. Muller | 2017-12-05 |
| 9685339 | Scalable split gate memory cell array | Jane A. Yater, Cheong Min Hong, Sung-Taeg Kang | 2017-06-20 |
| 9536614 | Common source architecture for split gate memory | Gilles J. Muller | 2017-01-03 |
| 9218889 | Multibit sense amplifier calibration | Tahmina Akhter, Gilles J. Muller | 2015-12-22 |
| 9111639 | Biasing split gate memory cell during power-off mode | Cheong Min Hong, Horacio P. Gasquet | 2015-08-18 |
| 9111629 | Smart charge pump configuration for non-volatile memories | Jeffrey C. Cunningham, Karthik Ramanan, Ross S. Scouller | 2015-08-18 |
| 9013927 | Sector-based regulation of program voltages for non-volatile memory (NVM) systems | Jeffrey C. Cunningham, Ross S. Scouller | 2015-04-21 |
| 8971147 | Control gate word line driver circuit for multigate memory | Gilles J. Muller | 2015-03-03 |
| 8885403 | Programming a split gate bit cell | Cheong Min Hong, Brian A. Winstead | 2014-11-11 |
| 8704587 | Configurable multistage charge pump using a supply detect scheme | Karthik Ramanan, Jeffrey C. Cunningham | 2014-04-22 |
| 8310877 | Read conditions for a non-volatile memory (NVM) | Jeffrey C. Cunningham, Thomas D. Cook, Stephen F. McGinty | 2012-11-13 |
| 7865797 | Memory device with adjustable read reference based on ECC and method thereof | Richard K. Eguchi | 2011-01-04 |
| 7843730 | Non-volatile memory with reduced charge fluence | — | 2010-11-30 |
| 7782664 | Method for electrically trimming an NVM reference cell | Horacio P. Gasquet, Richard K. Eguchi, Peter Kuhn | 2010-08-24 |
| 7742340 | Read reference technique with current degradation protection | Fuchen Mu, Marco A. Cabassi | 2010-06-22 |
| 7668018 | Electronic device including a nonvolatile memory array and methods of using the same | Gowrishankar L. Chindalore, Thomas Jew | 2010-02-23 |
| 7649781 | Bit cell reference device and methods thereof | Gowrishankar L. Chindalore | 2010-01-19 |
| 7624329 | Programming a memory device having error correction logic | Timothy J. Strauss | 2009-11-24 |
| 7564716 | Memory device with retained indicator of read reference level | David W. Chrudimsky, Xiaojie He | 2009-07-21 |
| 7545679 | Electrical erasable programmable memory transconductance testing | Richard K. Eguchi, Chen He | 2009-06-09 |
| 7259999 | Non-volatile memory cell array for improved data retention and method of operating thereof | Gowrishankar L. Chindalore, Paul A. Ingersoll, Peter Kuhn | 2007-08-21 |
| 6615391 | Current controlled multi-state parallel test for semiconductor device | Brian L. Brown, Jackson Leung, Pow Cheah Chang | 2003-09-02 |
| 6408411 | Two pass multi-state parallel test for semiconductor device | Brian L. Brown, Jackson Leung, Pow Cheah Chang | 2002-06-18 |
| 6381718 | Current controlled multi-state parallel test for semiconductor device | Brian L. Brown, Jackson Leung, Pow Cheah Chang | 2002-04-30 |