| D1081109 |
Needle threader |
— |
2025-07-01 |
| D1057080 |
Live shrimp hook |
— |
2025-01-07 |
| 11853111 |
System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction |
Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden +2 more |
2023-12-26 |
| 11644853 |
Power delivery system having low- and high-power power supplies |
Sonu Arora, Michael A. Nix, Moises E. Robinson |
2023-05-09 |
| 11567557 |
Electrical power operating states for core logic in a memory physical layer |
Sridhar V. Gada, Sonu Arora |
2023-01-31 |
| 11460879 |
System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction |
Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden +2 more |
2022-10-04 |
| 11455025 |
Power state transitions |
Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming L. So +2 more |
2022-09-27 |
| 10775874 |
Multi-tiered low power states |
Alexander J. Branover, Mihir Shaileshbhai Doctor, Evgeny Mintz, Fei Fei, Ming L. So +2 more |
2020-09-15 |
| 10712800 |
Aligning active and idle phases in a mixed workload computing platform |
Benjamin Tsien, Alexander J. Branover, Ming L. So, Philip Ng, Xiao Gang Zheng +4 more |
2020-07-14 |
| 8175528 |
Wireless mass storage flash memory |
Gregory A. Racino |
2012-05-08 |
| 7696784 |
Programmable logic device with multiple slice types |
Om P. Agrawal, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao |
2010-04-13 |
| 7685215 |
Fast-carry arithmetic circuit using a multi-input look-up table |
Brian C. Gaide |
2010-03-23 |
| 7675321 |
Dual-slice architectures for programmable logic devices |
Om P. Agrawal, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao |
2010-03-09 |
| 7605606 |
Area efficient routing architectures for programmable logic devices |
Ming H. Ding, Sajitha Wijesuriya, Jun Zhao, Om P. Agrawal, Barry Britton |
2009-10-20 |
| 7592834 |
Logic block control architectures for programmable logic devices |
Om P. Agrawal, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao |
2009-09-22 |
| 7564716 |
Memory device with retained indicator of read reference level |
Ronald J. Syzdek, David W. Chrudimsky |
2009-07-21 |
| 7397276 |
Logic block control architectures for programmable logic devices |
Om P. Agrawal, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao |
2008-07-08 |
| 7385417 |
Dual slice architectures for programmable logic devices |
Om P. Agrawal, Sajitha Wijesuriya, Barry Britton, Ming H. Ding, Jun Zhao |
2008-06-10 |
| 7378872 |
Programmable logic device architecture with multiple slice types |
Om P. Agrawal, Barry Britton, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao |
2008-05-27 |
| 7183798 |
Synchronous memory |
Sajitha Wijesuriya, Claudia A. Stanley, John Schadt |
2007-02-27 |
| 6653860 |
Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures |
Om P. Agrawal, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee |
2003-11-25 |
| 6348813 |
Scalable architecture for high density CPLD's having two-level hierarchy of routing resources |
Om P. Agrawal, Claudia A. Stanley, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein |
2002-02-19 |
| 6184713 |
Scalable architecture for high density CPLDS having two-level hierarchy of routing resources |
Om P. Agrawal, Claudia A. Stanley, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein |
2001-02-06 |
| 6150841 |
Enhanced macrocell module for high density CPLD architectures |
Om P. Agrawal, Claudia A. Stanley, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger +1 more |
2000-11-21 |