Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10819318 | Single event upset immune flip-flop utilizing a small-area highly resistive element | Phillip Johnson, John Schadt, David Onimus | 2020-10-27 |
| 8531222 | Phase locked loop circuit with selectable feedback paths | Richard Booth, Phillip Johnson, Yang Xu, Tawei David Li | 2013-09-10 |
| 8319521 | Safe programming of key information into non-volatile memory for a programmable logic device | Wei Han, Eric Lee, Zheng Chen, Warren Juenemann, Mose Wahlstrom | 2012-11-27 |
| 8314634 | Power control block with output glitch protection | Richard Booth, Yang Xu, Tawei David Li | 2012-11-20 |
| 7863931 | Flexible delay cell architecture | Fulong Zhang, Zhen Chen, William B. Andrews | 2011-01-04 |
| 7696784 | Programmable logic device with multiple slice types | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2010-04-13 |
| 7675321 | Dual-slice architectures for programmable logic devices | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2010-03-09 |
| 7650545 | Programmable interconnect for reconfigurable system-on-chip | Miron Abramovici, Yuzheng Ding, Harold Scholz | 2010-01-19 |
| 7605606 | Area efficient routing architectures for programmable logic devices | Ming H. Ding, Sajitha Wijesuriya, Jun Zhao, Om P. Agrawal, Xiaojie He | 2009-10-20 |
| 7599457 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits | Phillip Johnson, Zheng Chen | 2009-10-06 |
| 7592834 | Logic block control architectures for programmable logic devices | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2009-09-22 |
| 7554357 | Efficient configuration of daisy-chained programmable logic devices | Zheng Chen, Harold Scholz | 2009-06-30 |
| 7532646 | Distributed multiple-channel alignment scheme | Wai-Bor Leung, Akila Subramaniam | 2009-05-12 |
| 7397276 | Logic block control architectures for programmable logic devices | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2008-07-08 |
| 7385417 | Dual slice architectures for programmable logic devices | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2008-06-10 |
| 7378872 | Programmable logic device architecture with multiple slice types | Om P. Agrawal, Xiaojie He, Sajitha Wijesuriya, Ming H. Ding, Jun Zhao | 2008-05-27 |
| 7262630 | Programmable termination for single-ended and differential schemes | William B. Andrews, John Schadt, Mou C. Lin | 2007-08-28 |
| 7139288 | Protocol-independent packet delineation for backplane architecture | Francois Balay, Paul Langner, John B. McCluskey, Shakeel H. Peera | 2006-11-21 |
| 7034596 | Adaptive input logic for phase adjustments | William B. Andrews, Harold Scholz | 2006-04-25 |
| 6940779 | Programmable broadcast initialization of memory blocks | Zheng Chen, John Schadt | 2005-09-06 |
| 6873187 | Method and apparatus for controlling signal distribution in an electronic circuit | William B. Andrews, Xiaotao Chen, John Philip Fishburn, Harold Scholz | 2005-03-29 |
| 6483342 | Multi-master multi-slave system bus in a field programmable gate array (FPGA) | Ravikumar Charath, Zheng Chen, James F. Hoff, Cort D. Lansenderfer, Don McCarley +2 more | 2002-11-19 |
| 6472904 | Double data rate input and output in a programmable logic device | William B. Andrews | 2002-10-29 |
| 6216191 | Field programmable gate array having a dedicated processor interface | Alan Cunningham, Wai-Bor Leung, Richard G. Stuby, Jr., James A. Thompson | 2001-04-10 |
| 6064225 | Global signal distribution with reduced routing tracks in an FPGA | William B. Andrews, Kai-Kit Ngai, Gary P. Powell, Satwant Singh, Carolyn W. Spivak +1 more | 2000-05-16 |