Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8977917 | Highly secure and extensive scan testing of integrated circuits | Wei Han, Eric Lee, Jie Qin, Shankar Durgamahanthi, Kanad Chakraborty +1 more | 2015-03-10 |
| 8816718 | Variable response mode for synchronous data read | Wei Han, Warren Juenemann | 2014-08-26 |
| 8522126 | Blocking memory readback in a programmable logic device | Rohith Sood, Loren L. McLaury | 2013-08-27 |
| 8477549 | Triggered sense amplifier | Rohith Sood, Loren L. McLaury | 2013-07-02 |
| 8461894 | Low-power configurable delay element | Fulong Zhang, Chien-Kuang Chen, John Schadt | 2013-06-11 |
| 8384428 | Pre-configuration programmability of I/O circuitry | William B. Andrews | 2013-02-26 |
| 8368424 | Programmable logic device wakeup using a general purpose input/output port | Wei Han, Warren Juenemann, Eric Lee | 2013-02-05 |
| 8351287 | Bitline floating circuit for memory power reduction | Rohith Sood, Fabiano Fontana | 2013-01-08 |
| 8319521 | Safe programming of key information into non-volatile memory for a programmable logic device | Wei Han, Barry Britton, Eric Lee, Warren Juenemann, Mose Wahlstrom | 2012-11-27 |
| 8248136 | Low-power, glitch-less, configurable delay element | Fulong Zhang, Chien-Kuang Chen, John Schadt | 2012-08-21 |
| 7831754 | Multiple communication channel configuration systems and methods | Glen E. Offord, Jamie Freed | 2010-11-09 |
| 7808405 | Efficient bitstream compression | — | 2010-10-05 |
| 7620839 | Jitter tolerant delay-locked loop circuit | Phillip Johnson, Fulong Zhang | 2009-11-17 |
| 7599457 | Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits | Phillip Johnson, Barry Britton | 2009-10-06 |
| 7586344 | Dynamic delay or advance adjustment of oscillating signal phase | Richard Booth, Phillip Johnson | 2009-09-08 |
| 7554357 | Efficient configuration of daisy-chained programmable logic devices | Barry Britton, Harold Scholz | 2009-06-30 |
| 7511641 | Efficient bitstream compression | — | 2009-03-31 |
| 7177221 | Initializing memory blocks | Nhon Hoa Nguyen, Hemanshu T. Vernenker, Allen White, Christopher Hume | 2007-02-13 |
| 7161862 | Low power asynchronous sense amp | Mou C. Lin, Larry R. Fenstermaker | 2007-01-09 |
| 7009433 | Digitally controlled delay cells | Fulong Zhang, William B. Andrews, Phillip Johnson, Hal Scholz, John Schadt | 2006-03-07 |
| 6975137 | Programmable logic devices with integrated standard-cell logic blocks | John Schadt, William B. Andrews, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus +3 more | 2005-12-13 |
| 6940779 | Programmable broadcast initialization of memory blocks | John Schadt, Barry Britton | 2005-09-06 |
| 6903574 | Memory access via serial memory interface | Fulong Zhang, Harold Scholz | 2005-06-07 |
| 6882555 | Bi-directional buffering for memory data lines | Larry R. Fenstermaker, Gregory S. Cartney | 2005-04-19 |
| 6870395 | Programmable logic devices with integrated standard-cell logic blocks | John Schadt, William B. Andrews, Anthony K. Myers, David A. Rhein, Warren L. Ziegenfus +3 more | 2005-03-22 |