Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8971146 | Dual-port SRAM with bit line clamping | Brad Sharpe-Geisler, Timothy Scott Swensen, Sam Tsai | 2015-03-03 |
| 8553463 | Voltage discharge circuit having divided discharge current | Robert G. Pollachek, Loren L. McLaury | 2013-10-08 |
| 8451679 | Dual-port SRAM with bit line clamping | Brad Sharpe-Geisler, Timothy Scott Swensen, Sam Tsai | 2013-05-28 |
| 8351287 | Bitline floating circuit for memory power reduction | Rohith Sood, Zheng Chen | 2013-01-08 |
| 7957208 | Flexible memory architectures for programmable logic devices | Howard Tang, David L. Rutledge, Om P. Agrawal, Henry Law | 2011-06-07 |
| 7724029 | Power management for integrated circuits such as programmable logic devices | Satwant Singh, David Chang | 2010-05-25 |
| 7702977 | Programmable logic devices with custom identification systems and methods | Howard Tang, Om P. Agrawal | 2010-04-20 |
| 7560953 | Power management systems and methods for programmable logic devices | Satwant Singh, David Chang | 2009-07-14 |
| 7554358 | Programmable logic devices with user non-volatile memory | Henry Law, Howard Tang, Om P. Agrawal, David L. Rutledge | 2009-06-30 |
| 7546498 | Programmable logic devices with custom identification systems and methods | Howard Tang, Om P. Agrawal | 2009-06-09 |
| 7495970 | Flexible memory architectures for programmable logic devices | Howard Tang, David L. Rutledge, Om P. Agrawal, Henry Law | 2009-02-24 |
| 7459931 | Programmable logic devices with transparent field reconfiguration | Howard Tang, Henry Law, David L. Rutledge, Om P. Agrawal | 2008-12-02 |
| 7378873 | Programmable logic device providing a serial peripheral interface | Howard Tang, Om P. Agrawal, David L. Rutledge | 2008-05-27 |
| RE40311 | Zero-power programmable memory cell | Sunil Mehta | 2008-05-13 |
| 7313025 | Flash memory erase verification systems and methods | Hok-tung Wong | 2007-12-25 |
| 7187586 | Flash memory erase verification systems and methods | Hok-tung Wong | 2007-03-06 |
| 6838904 | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation | Om P. Agrawal, Gilles Bosco | 2005-01-04 |
| 6650142 | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use | Om P. Agrawal, Gilles Bosco | 2003-11-18 |
| 6611463 | Zero-power programmable memory cell | Sunil Mehta | 2003-08-26 |
| 6489806 | Zero-power logic cell for use in programmable logic devices | Sunil Mehta | 2002-12-03 |
| 6133769 | Phase locked loop with a lock detector | Mathew A. Rybicki, Ammisetti Prasad | 2000-10-17 |
| 5982683 | Enhanced method of testing semiconductor devices having nonvolatile elements | James A. Watson, Jenny Chui, Steve Choi, Benjamin Shui Chor Lau | 1999-11-09 |
| 5748525 | Array cell circuit with split read/write line | Jack T. Wong, Susan Xuan Nguyen | 1998-05-05 |
| 5668488 | Input buffer for a high density programmable logic device | Bradley A. Sharpe-Geisler | 1997-09-16 |
| 5568066 | Sense amplifier and or gate for a high density programmable logic device | Bradley A. Sharpe-Geisler | 1996-10-22 |