Issued Patents All Time
Showing 1–25 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373117 | Selectively powered embedded memory systems and methods | Maryam Shahbazi, Loren L. McLaury | 2025-07-29 |
| 11907033 | Adaptive power-on-reset generator systems and methods for programmable logic devices | Chwei-Po Chew | 2024-02-20 |
| 10884452 | Low-speed bus triggering methods and circuitry | — | 2021-01-05 |
| 10764026 | Acoustic gesture recognition systems and methods | — | 2020-09-01 |
| 10466738 | Low-speed bus time stamp methods and circuitry | — | 2019-11-05 |
| 10326627 | Clock recovery and data recovery for programmable logic devices | — | 2019-06-18 |
| 10148472 | Clock recovery and data recovery for programmable logic devices | — | 2018-12-04 |
| RE39510 | FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections | Om P. Agrawal, Herman M. Chang, Bai Nguyen | 2007-03-13 |
| 7028281 | FPGA with register-intensive architecture | Om P. Agrawal | 2006-04-11 |
| 7000212 | Hierarchical general interconnect architecture for high density FPGA'S | Om P. Agrawal | 2006-02-14 |
| 6919736 | Field programmable gate array having embedded memory with configurable depth and width | Om P. Agrawal, Bai Nguyen, Yu-Hua Huang, Jack T. Wong | 2005-07-19 |
| 6870391 | Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility | — | 2005-03-22 |
| 6798244 | Output buffer with overvoltage protection | — | 2004-09-28 |
| 6760209 | Electrostatic discharge protection circuit | — | 2004-07-06 |
| 6753696 | Programmable optimized-distribution logic allocator for a high-density complex PLD | Om P. Agrawal, Nicholas A. Schmitz | 2004-06-22 |
| 6725442 | Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device | Richard T. Cote, Brenda Nguyen, Xuan Dai Pham | 2004-04-20 |
| 6720755 | Band gap reference circuit | — | 2004-04-13 |
| 6714048 | Input buffer with voltage clamping for compatibility | — | 2004-03-30 |
| 6714043 | Output buffer having programmable drive current and output voltage limits | — | 2004-03-30 |
| 6657458 | Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility | — | 2003-12-02 |
| 6621298 | Variable grain architecture for FPGA integrated circuits | Om P. Agrawal, Herman M. Chang, Giap H. Tran | 2003-09-16 |
| 6590415 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Om P. Agrawal, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-07-08 |
| 6531890 | Programmable optimized-distribution logic allocator for a high-density complex PLD | Om P. Agrawal, Nicholas A. Schmitz | 2003-03-11 |
| 6526558 | Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources | Om P. Agrawal, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2003-02-25 |
| 6470485 | Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device | Richard T. Cote, Brenda Nguyen, Xuan Dai Pham | 2002-10-22 |