Issued Patents All Time
Showing 51–75 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6107823 | Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits | Om P. Agrawal, Giap H. Tran | 2000-08-22 |
| 6100715 | Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources | Om P. Agrawal, Herman M. Chang, Bai Nguyen, Giap H. Tran | 2000-08-08 |
| 6097664 | Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan | Bai Nguyen, Herman M. Chang, Om P. Agrawal | 2000-08-01 |
| 6097212 | Variable grain architecture for FPGA integrated circuits | Om P. Agrawal, Herman M. Chang, Giap H. Tran | 2000-08-01 |
| 6091595 | Electrostatic discharge (ESD) protection for NMOS pull up transistors of a 5.0 volt compatible output buffer using 2.5 volt process transistors | — | 2000-07-18 |
| 6081473 | FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode | Om P. Agrawal, Herman M. Chang, Bai Nguyen | 2000-06-27 |
| 6072351 | Output buffer for making a 5.0 volt compatible input/output in a 2.5 volt semiconductor process | — | 2000-06-06 |
| 6043969 | Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors | — | 2000-03-28 |
| 6034544 | Programmable input/output block (IOB) in FPGA integrated circuits | Om P. Agrawal, Herman M. Chang, Bai Nguyen | 2000-03-07 |
| 6031365 | Band gap reference using a low voltage power supply | — | 2000-02-29 |
| 6028758 | Electrostatic discharge (ESD) protection for a 5.0 volt compatible input/output (I/O) in a 2.5 volt semiconductor process | — | 2000-02-22 |
| 5990702 | Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits | Om P. Agrawal, Giap H. Tran | 1999-11-23 |
| 5986480 | Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA) | — | 1999-11-16 |
| 5982193 | Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits | Om P. Agrawal, John Tobey, Giap H. Tran | 1999-11-09 |
| 5912550 | Power converter with 2.5 volt semiconductor process components | — | 1999-06-15 |
| 5905385 | Memory bits used to couple look up table inputs to facilitate increased availability to routing resources particularly for variable sized look up tables for a field programmable gate array (FPGA) | — | 1999-05-18 |
| 5844912 | Fast verify for CMOS memory cells | — | 1998-12-01 |
| 5818254 | Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices | Om P. Agrawal | 1998-10-06 |
| 5811987 | Block clock and initialization circuit for a complex high density PLD | Benjamin H. Ashmore, Jr., Jeffery Mark Marshall, Bryon Irwin Moyer, John D. Porter, Nicholas A. Schmitz | 1998-09-22 |
| 5808942 | Field programmable gate array (FPGA) having an improved configuration memory and look up table | — | 1998-09-15 |
| 5796295 | Reference for CMOS memory cell having PMOS and NMOS transistors with a common floating gate | — | 1998-08-18 |
| 5789939 | Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device | Om P. Agrawal | 1998-08-04 |
| 5781030 | Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD | Om P. Agrawal | 1998-07-14 |
| 5760609 | Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device | — | 1998-06-02 |
| 5751164 | Programmable logic device with multi-level power control | Bryon Irwin Moyer | 1998-05-12 |