Issued Patents All Time
Showing 76–100 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5739713 | Deconvolution input buffer compensating for capacitance of a switch matrix of a high density programmable logic device | — | 1998-04-14 |
| 5736888 | Capacitance elimination circuit which provides current to a node in a circuit to eliminate the effect of parasitic capacitance at the node | — | 1998-04-07 |
| 5723984 | Field programmable gate array (FPGA) with interconnect encoding | — | 1998-03-03 |
| 5719516 | Lock generator circuit for use with a dual edge register that provides a separate enable for each use of an input clock signal | — | 1998-02-17 |
| 5668488 | Input buffer for a high density programmable logic device | Fabiano Fontana | 1997-09-16 |
| 5646901 | CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors | Jonathan Lin, Radu Barsan | 1997-07-08 |
| 5638018 | P-type flip-flop | — | 1997-06-10 |
| 5596524 | CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase | Jonathan Lin | 1997-01-21 |
| 5594687 | Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase | Jonathan Lin, Radu Barsan | 1997-01-14 |
| 5589782 | Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions | — | 1996-12-31 |
| 5583451 | Polarity control circuit which may be used with a ground bounce limiting buffer | — | 1996-12-10 |
| 5570046 | Lead frame with noisy and quiet V.sub.SS and V.sub.DD leads | — | 1996-10-29 |
| 5568066 | Sense amplifier and or gate for a high density programmable logic device | Fabiano Fontana | 1996-10-22 |
| 5521529 | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation | Om P. Agrawal, Nicholas A. Schmitz, Bryon Irwin Moyer | 1996-05-28 |
| 5495195 | Output buffer for a high density programmable logic device | Fabiano Fontana | 1996-02-27 |
| 5491433 | Cascode array cell partitioning for a sense amplifier of a programmable logic device | — | 1996-02-13 |
| 5469088 | Cascade array cell partitioning for a sense amplifier of a programmable logic device | — | 1995-11-21 |
| 5457404 | Zero-power OR gate | — | 1995-10-10 |
| 5438277 | Ground bounce isolated output buffer | — | 1995-08-01 |
| 5410268 | Latching zero-power sense amplifier with cascode | — | 1995-04-25 |
| 5406139 | Input buffer utilizing a cascode to provide a zero power TTL to CMOS input with high speed switching | — | 1995-04-11 |
| 5084404 | Gate array structure and process to allow optioning at second metal mask only | — | 1992-01-28 |
| 5023701 | Gate array structure and process to allow optioning at second metal mask only | — | 1991-06-11 |
| 4855711 | Impact detection apparatus | David Harrop, Valli R. Sharpe-Geisler | 1989-08-08 |
| 4740485 | Method for forming a fuse | — | 1988-04-26 |