HC

Herman M. Chang

VA Vantis: 16 patents #4 of 24Top 20%
LS Lattice Semiconductor: 7 patents #65 of 544Top 15%
AM AMD: 1 patents #5,683 of 9,279Top 65%
HM Holtek Microelectronics: 1 patents #16 of 54Top 30%
Overall (All Time): #165,537 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
RE39510 FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2007-03-13
6621298 Variable grain architecture for FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2003-09-16
6590415 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2003-07-08
6526558 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2003-02-25
6380759 Variable grain architecture for FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2002-04-30
6292930 Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2001-09-18
6275064 Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2001-08-14
6249144 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2001-06-19
6216257 FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen 2001-04-10
6211695 FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2001-04-03
6204686 Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2001-03-20
6181163 FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2001-01-30
6163168 Efficient interconnect network for use in FPGA device having variable grain architecture Bai Nguyen, Om P. Agrawal, Bradley A. Sharpe-Geisler, Jack T. Wong 2000-12-19
6154051 Tileable and compact layout for super variable grain blocks within FPGA device Bai Nguyen, Om P. Agrawal, Bradley A. Sharpe-Geisler, Jack T. Wong, Giap H. Tran 2000-11-28
6150842 Variable grain architecture for FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2000-11-21
6130551 Synthesis-friendly FPGA architecture with variable length and variable timing interconnect Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran, Bai Nguyen 2000-10-10
6127843 Dual port SRAM memory for run time use in FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2000-10-03
6124730 Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2000-09-26
6100715 Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen, Giap H. Tran 2000-08-08
6097664 Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan Bai Nguyen, Bradley A. Sharpe-Geisler, Om P. Agrawal 2000-08-01
6097212 Variable grain architecture for FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Giap H. Tran 2000-08-01
6081473 FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2000-06-27
6034544 Programmable input/output block (IOB) in FPGA integrated circuits Om P. Agrawal, Bradley A. Sharpe-Geisler, Bai Nguyen 2000-03-07
5424740 Digital-to-analog converter with a Johnson code generator Ning Chung-Ho 1995-06-13
5315174 Programmable output slew rate control Melvin Chan 1994-05-24