Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12136879 | Dual-output switched-capacitor power converter | — | 2024-11-05 |
| 12126259 | High voltage stage for switching regulator | Haritha Chanda | 2024-10-22 |
| 11855535 | High voltage stage for switching regulator | Haritha Chanda | 2023-12-26 |
| 10153279 | Compact and reliable changeable negative voltage transmission circuit | Fei Xu, Jinling Wang, Benjamin Shui Chor Lau | 2018-12-11 |
| 10115453 | Integrated circuits with SRAM devices having read assist circuits and methods for operating such circuits | Zhihong Luo, Qi Chen, Joanne Wang, Yi-Chung Liang, Fei Xu +1 more | 2018-10-30 |
| 9843326 | Wide range level shifter for low voltage input applications | Fei Xu, On Auyeung, Qi Chen, Zhihong Luo, Sui Chor Benjamin Lau | 2017-12-12 |
| 9837170 | Systems and methods for testing performance of memory modules | Benjamin Shui Chor Lau, Chou-Te Kang, Yao-Hsien Huang | 2017-12-05 |
| 9806087 | Low cost high performance EEPROM device | Chandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Yoke Weng Tam | 2017-10-31 |
| 9659947 | Low cost high performance EEPROM device | Chandrasekar Venkataramani, Qiuji Zhao, Koe Sun Pak, Yoke Weng Tam | 2017-05-23 |
| 9489004 | Bandgap reference voltage generator circuits | Zhiqi Huang, Yoke Weng Tam, Benjamin Shui Chor Lau | 2016-11-08 |
| 9411919 | Method and apparatus for bitcell modeling | Zhiqi Huang, Yoke Weng Tam, Benjamin Shui Chor Lau | 2016-08-09 |
| 9361992 | Low voltage semiconductor memory device and method of operation | Yoke Weng Tam, Zhiqi Huang, Benjamin Shui Chor Lau | 2016-06-07 |
| 8803590 | High speed low power fuse circuit | Zhihong Luo, On Au Yeung, Benjamin Shui Chor Lau | 2014-08-12 |
| 7787326 | Programmable logic device with a multi-data rate SDRAM interface | Brad Sharpe-Geisler, Om P. Agrawal, Kiet Truong, Giap H. Tran | 2010-08-31 |
| 7558143 | Programmable logic device with power-saving architecture | Henry Law, Brad Sharpe-Geisler, Giap H. Tran, Kiet Truong | 2009-07-07 |
| 7459935 | Programmable logic devices with distributed memory | Om P. Agrawal, Brad Sharpe-Geisler, Jye-Yuh Lee | 2008-12-02 |
| 7411419 | Input/output systems and methods | Kiet Truong, Brad Sharpe-Geisler, Giap H. Tran | 2008-08-12 |
| 7376037 | Programmable logic device with power-saving architecture | Henry Law, Brad Sharpe-Geisler, Giap H. Tran, Kiet Truong | 2008-05-20 |
| 7355441 | Programmable logic devices with distributed memory and non-volatile memory | Om P. Agrawal, Brad Sharpe-Geisler, Jye-Yuh Lee | 2008-04-08 |
| 7342838 | Programmable logic device with a double data rate SDRAM interface | Brad Sharpe-Geisler, Om P. Agrawal, Kiet Truong, Giap H. Tran | 2008-03-11 |
| RE39510 | FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections | Om P. Agrawal, Herman M. Chang, Bradley A. Sharpe-Geisler | 2007-03-13 |
| 7098685 | Scalable serializer-deserializer architecture and programmable interface | Om P. Agrawal, Kuang Chi, Brad Sharpe-Geisler, Giap H. Tran | 2006-08-29 |
| 7061269 | I/O buffer architecture for programmable devices | Om P. Agrawal, Giap H. Tran, Kiet Truong | 2006-06-13 |
| 6919736 | Field programmable gate array having embedded memory with configurable depth and width | Om P. Agrawal, Bradley A. Sharpe-Geisler, Yu-Hua Huang, Jack T. Wong | 2005-07-19 |
| 6590415 | Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources | Om P. Agrawal, Bradley A. Sharpe-Geisler, Herman M. Chang, Giap H. Tran | 2003-07-08 |