Issued Patents All Time
Showing 25 most recent of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373117 | Selectively powered embedded memory systems and methods | Maryam Shahbazi, Bradley A. Sharpe-Geisler | 2025-07-29 |
| 11316521 | Power supply regulation for programmable logic devices | — | 2022-04-26 |
| 10417078 | Deterministic read back and error detection for programmable logic devices | Brad Sharpe-Geisler | 2019-09-17 |
| 9542993 | Leakage-current abatement circuitry for memory arrays | — | 2017-01-10 |
| 9286952 | SRAM with two-level voltage regulator | — | 2016-03-15 |
| 9191022 | Leakage-current abatement circuitry for memory arrays | — | 2015-11-17 |
| 8553463 | Voltage discharge circuit having divided discharge current | Robert G. Pollachek, Fabiano Fontana | 2013-10-08 |
| 8522126 | Blocking memory readback in a programmable logic device | Zheng Chen, Rohith Sood | 2013-08-27 |
| 8477549 | Triggered sense amplifier | Rohith Sood, Zheng Chen | 2013-07-02 |
| 8059470 | Flash memory array with independently erasable sectors | David L. Rutledge | 2011-11-15 |
| 7944765 | Programmable logic device with built in self test | Wei Han, Yoshita Yerramilli, Warren Juenemann | 2011-05-17 |
| 7636259 | Flash memory array with independently erasable sectors | David L. Rutledge | 2009-12-22 |
| 7630259 | Programmable logic device with built in self test | Wei Han, Yoshita Yerramilli, Warren Juenemann | 2009-12-08 |
| 7605602 | Low-power output driver buffer circuit | Nathan Green | 2009-10-20 |
| 7512015 | Negative voltage blocking for embedded memories | — | 2009-03-31 |
| 7484144 | Testing embedded memory in an integrated circuit | Wei Han | 2009-01-27 |
| 7411414 | Single-ended output driver buffer | Nathan Green | 2008-08-12 |
| 6917536 | Memory access circuit and method for reading and writing data with the same clock signal | David J. Wicker | 2005-07-12 |
| 6738306 | SRAM cell with single-ended and differential read/write ports | — | 2004-05-18 |
| 6625064 | Fast, low power, write scheme for memory circuits using pulsed off isolation device | Donald M. Morgan | 2003-09-23 |
| 6549481 | Power up initialization circuit responding to an input signal | — | 2003-04-15 |
| 6452866 | Method and apparatus for multiple latency synchronous dynamic random access memory | — | 2002-09-17 |
| 6424594 | Method and apparatus for multiple latency synchronous dynamic random access memory | — | 2002-07-23 |
| 6363025 | Power up initialization circuit responding to an input signal | — | 2002-03-26 |
| 6359831 | Method and apparatus for multiple latency synchronous dynamic random access memory | — | 2002-03-19 |