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Systems and methods for controlling power in semiconductor circuits |
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Circuit layout for improved performance while preserving or improving density |
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EEPROM device with voltage-limiting charge pump circuit |
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Scalable architecture for high density CPLD's having two-level hierarchy of routing resources |
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Scalable architecture for high density CPLDS having two-level hierarchy of routing resources |
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Enhanced macrocell module for high density CPLD architectures |
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Flexible synchronous and asynchronous circuits for a very high density programmable logic device |
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2000-02-22 |
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High density programmable logic device |
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1999-02-09 |
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Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
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1998-09-22 |
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Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
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1996-02-06 |
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Logic allocator for a programmable logic device |
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1996-01-16 |
| 5457409 |
Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
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1995-10-10 |
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Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
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1993-07-06 |
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Multiple array high performance programmable logic device family |
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1991-05-14 |
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Flexible, programmable cell array interconnected by a programmable switch matrix |
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