Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7366032 | Multi-ported register cell with randomly accessible history | Jan-Michael Huber, Michael Kevin Ciraula | 2008-04-29 |
| 7355881 | Memory array with global bitline domino read/write scheme | Floyd L. Dankert, Victor F. Andrade, Randal L. Posey, Michael Kevin Ciraula, Alexander W. Schaefer +4 more | 2008-04-08 |
| 7315054 | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit | James C. Pattison | 2008-01-01 |
| 7124236 | Microprocessor including bank-pipelined cache with asynchronous data blocks | Teik-Chung Tan, Mitchell Alsup | 2006-10-17 |
| 6670843 | Method and apparatus for sensing a programming state of fuses | Gregory A. Constant | 2003-12-30 |
| 5869981 | High density programmable logic device | Om P. Agrawal, George Landers, Nicholas A. Schmitz, Kerry A. Ilgenstein | 1999-02-09 |
| 5764078 | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix | Om P. Agrawal | 1998-06-09 |
| 5612631 | An I/O macrocell for a programmable logic device | Om P. Agrawal | 1997-03-18 |
| 5594365 | Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device | Om P. Agrawal | 1997-01-14 |
| 5581126 | Interlaced layout configuration for differential pairs of interconnect lines | — | 1996-12-03 |
| 5485104 | Logic allocator for a programmable logic device | Om P. Agrawal, Kerry A. Ilgenstein | 1996-01-16 |
| 5457409 | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices | Om P. Agrawal, Kerry A. Ilgenstein | 1995-10-10 |
| 5436514 | High speed centralized switch matrix for a programmable logic device | Om P. Agrawal | 1995-07-25 |
| 5307352 | Switch matrix multiplexers | — | 1994-04-26 |
| 5225719 | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix | Om P. Agrawal, George Landers, Nicholas A. Schmitz, Kerry A. Ilgenstein | 1993-07-06 |
| 5015884 | Multiple array high performance programmable logic device family | Om P. Agrawal, George Landers, Nicholas A. Schmitz, Kerry A. Ilgenstein | 1991-05-14 |
| 4963768 | Flexible, programmable cell array interconnected by a programmable switch matrix | Om P. Agrawal, Kerry A. Ilgenstein, Michael J. Wright, Arthur H. Khu | 1990-10-16 |
| 4633429 | Partial memory selection using a programmable decoder | Alan Lewandowski | 1986-12-30 |
| 4490627 | Schmitt trigger circuit | Frank Miller | 1984-12-25 |
| 4484308 | Serial data mode circuit for a memory | Alan Lewandowski | 1984-11-20 |
| RE31662 | Output buffer with voltage sustainer circuit | Roger I. Kung | 1984-09-04 |
| RE31663 | Dynamic output buffer | Roger I. Kung | 1984-09-04 |
| 4455493 | Substrate bias pump | Bruce L. Morton | 1984-06-19 |
| 4401897 | Substrate bias voltage regulator | William L. Martino, Jr. | 1983-08-30 |
| 4356412 | Substrate bias regulator | Rodney C. Tesch | 1982-10-26 |