Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11861781 | Graphics processing units with power management and latency reduction | Sreekanth GODEY, Ashkan Hosseinzadeh Namin, Seunghun Jin | 2024-01-02 |
| 10963388 | Prefetching in a lower level exclusive cache hierarchy | Vikas Sinha, Tarun Nakra | 2021-03-30 |
| 9727340 | Hybrid tag scheduler to broadcast scheduler entry tags for picked instructions | Michael Achenbach, Gregory W. Smaus, Ganesh Venkataramanan, Emil Talpes | 2017-08-08 |
| 9395988 | Micro-ops including packed source and destination fields | Bradley Gene Burgess, Ravi Iyengar | 2016-07-19 |
| 9256544 | Way preparation for accessing a cache | Matthew M. Crum | 2016-02-09 |
| 7783692 | Fast flag generation | Wing Shek Wong, Michael E. Tuuk | 2010-08-24 |
| 7610476 | Multiple control sequences per row of microcode ROM | Gregory W. Smaus | 2009-10-27 |
| 7584237 | Fast hardware divider | Michael E. Tuuk, Wing Shek Wong | 2009-09-01 |
| 7464255 | Using a shuffle unit to implement shift operations in a processor | Kelvin D. Goveas | 2008-12-09 |
| 7380070 | Organization of dirty bits for a write-back cache | — | 2008-05-27 |
| 7124236 | Microprocessor including bank-pipelined cache with asynchronous data blocks | Mitchell Alsup, Jerry D. Moench | 2006-10-17 |
| 7028068 | Alternate phase dual compression-tree multiplier | Kelvin D. Goveas | 2006-04-11 |
| 6823427 | Sectored least-recently-used cache replacement | Benjamin T. Sander, Adam Raymond DULEY | 2004-11-23 |
| 6760392 | Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios | Brian D. McMinn | 2004-07-06 |
| 6725337 | Method and system for speculatively invalidating lines in a cache | Benjamin T. Sander | 2004-04-20 |
| 6571318 | Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism | Benjamin T. Sander, William A. Hughes, Sridhar Subramanian | 2003-05-27 |
| 6424688 | Method to transfer data in a system with multiple clock domains using clock skipping techniques | Derrick R. Meyer, Brian D. McMinn | 2002-07-23 |
| 5920710 | Apparatus and method for modifying status bits in a reorder buffer with a large speculative state | Thang M. Tran | 1999-07-06 |
| 5870579 | Reorder buffer including a circuit for selecting a designated mask corresponding to an instruction that results in an exception | — | 1999-02-09 |
| 5815031 | High density dynamic bus routing scheme | Stephen C. Kromer, Joe Peters | 1998-09-29 |