Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373210 | Transfer buffer between a scalar pipeline and vector pipeline | David William Kravitz, Andrew Hanselman | 2025-07-29 |
| 12293192 | Bundling and dynamic allocation of register blocks for vector instructions | David William Kravitz, Alexandre Solomatnikov | 2025-05-06 |
| 12204458 | Translation lookaside buffer probing prevention | — | 2025-01-21 |
| 9836304 | Cumulative confidence fetch throttling | Marvin Denman, James David Dundas, Jeff Rupley | 2017-12-05 |
| 9588770 | Dynamic rename based register reconfiguration of a vector register file | Ashraf Ahmed, Ravi Iyengar | 2017-03-07 |
| 9424041 | Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions | Ravi Iyengar, Sandeep Kumar Dubey | 2016-08-23 |
| 9395988 | Micro-ops including packed source and destination fields | Teik-Chung Tan, Ravi Iyengar | 2016-07-19 |
| 8736308 | Pipeline power gating | Daniel W. Bailey, Aaron Stanley Rogers, James J. Montanaro, Peter J. Hannan | 2014-05-27 |
| 7921293 | Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment | Michael Kozuch, James A. Sutton, David W. Grawrock, Gilbert Neiger, Richard Uhlig +5 more | 2011-04-05 |
| 7024555 | Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment | Michael Kozuch, James A. Sutton, David W. Grawrock, Gilbert Neiger, Richard Uhlig +5 more | 2006-04-04 |
| 6950904 | Cache way replacement technique | Todd D. Erdner, Heather L. Hanson | 2005-09-27 |
| 6519683 | System and method for instruction cache re-ordering | Nicholas Samra | 2003-02-11 |
| 6477640 | Apparatus and method for predicting multiple branches and performing out-of-order branch resolution | Jeffrey P. Rupley, II, Marvin Denman, David C. Holloway | 2002-11-05 |
| 6202130 | Data processing system for processing vector data and method therefor | Hunter Ledbetter Scales, III, Keith E. Diefendorff, Brett Olsson, Pradeep Kumar Dubey, Ronald Ray Hochsprung +4 more | 2001-03-13 |
| 6157999 | Data processing system having a synchronizing link stack and method thereof | Paul C. Rossbach, Albert R. Kennedy, Jeffrey P. Rupley, II | 2000-12-05 |
| 6157998 | Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers | Jeffrey P. Rupley, II, Marvin Denman, David C. Holloway | 2000-12-05 |
| 5642493 | Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction | — | 1997-06-24 |
| 5500943 | Data processor with rename buffer and FIFO buffer for in-order instruction completion | Ying-wai Ho | 1996-03-19 |
| 5448744 | Integrated circuit microprocessor with programmable chip select logic | James B. Eifert, John J. Vaglica, James C. Smallwood, Mark W. McDermott, Hiroyuki Sugiyama +1 more | 1995-09-05 |
| 5408428 | Programmable bit cell | Jeffrey Slaton | 1995-04-18 |
| 5392228 | Result normalizer and method of operation | Timothy A. Elliott, Christopher H. Olson, Terence M. Potter | 1995-02-21 |
| 5361392 | Digital computing system with low power mode and special bus cycle therefor | Antone L. Fourcroy, Mark W. McDermott, John P. Dunn | 1994-11-01 |
| 5329621 | Microprocessor which optimizes bus utilization based upon bus speed | James B. Eifert, Michael S. Taborn | 1994-07-12 |
| 5072365 | Direct memory access controller using prioritized interrupts for varying bus mastership | James B. Eifert, John P. Dunn | 1991-12-10 |
| 5034922 | Intelligent electrically erasable, programmable read-only memory with improved read latency | — | 1991-07-23 |