Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7221188 | Logic circuitry | Andrew A. Bjorksten, Khoi Mai | 2007-05-22 |
| 6157999 | Data processing system having a synchronizing link stack and method thereof | Albert R. Kennedy, Jeffrey P. Rupley, II, Bradley Gene Burgess | 2000-12-05 |
| 5974535 | Method and system in data processing system of permitting concurrent processing of instructions of a particular type | Chih-Jui Peng, Daniel C. Chow, Terence M. Potter | 1999-10-26 |
| 5901307 | Processor having a selectively configurable branch prediction unit that can access a branch prediction utilizing bits derived from a plurality of sources | Terence M. Potter, Thomas L. Thomas, Jr. | 1999-05-04 |
| 5784606 | Method and system in a superscalar data processing system for the efficient handling of exceptions | Thomas Hoy, Terence M. Potter | 1998-07-21 |
| 5765017 | Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers | Thomas Hoy, Terence M. Potter | 1998-06-09 |
| 5765221 | Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register | Chin-Cheng Kau, David S. Levitan | 1998-06-09 |
| 5715427 | Semi-associative cache with MRU/LRU replacement | David D. Barrera, Bahador Rastegar | 1998-02-03 |
| 5553255 | Data processor with programmable levels of speculative instruction fetching and method of operation | Danny K. Jain, David S. Levitan | 1996-09-03 |
| 5550995 | Memory cache with automatic alliased entry invalidation and method of operation | David D. Barrera, Bahador Rastegar | 1996-08-27 |
| 5530824 | Address translation circuit | Chih-Jiu Peng | 1996-06-25 |
| 5499204 | Memory cache with interlaced data and method of operation | David D. Barrera, Dave S. Levitan, Bahador Rastegar | 1996-03-12 |
| 5291076 | Decoder/comparator and method of operation | Jeffrey Todd Bridges, Jeffrey E. Maguire | 1994-03-01 |
| 5272660 | Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor | — | 1993-12-21 |
| 5237525 | In a data processor an SRT divider having a negative divisor sticky detection circuit | — | 1993-08-17 |