Nicholas Samra — 22 Patents at Intel

Nicholas Samra has been granted 22 US patents while listed as an inventor at Intel. The first was granted in 1995 and the most recent in October 2014. Nicholas Samra ranks #189,202 of 4,157,543 US inventors in our database (top 4.6%). Patent records list Nicholas Samra in Austin, TX, US.

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8860199	Multi-die processor	Bryan Black, M. Clair Webb	2014-10-14	$15,559,000
8694976	Sleep state mechanism for virtual multithreading	—	2014-04-08	$30,134,000
8219836	Methods and apparatus to monitor instruction types and control power consumption within a processor	Andrew Shane Huang, Namratha Jaisimha	2012-07-10	$16,128,000
7669203	Virtual multithreading translation mechanism including retrofit capability	Andrew Shane Huang	2010-02-23	$16,403,000
7653904	System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected	—	2010-01-26	$14,937,000
7398372	Fusing load and alu operations	Stephan Jourdan, David J. Sager, Glenn J. Hinton	2008-07-08	$24,723,000
7308563	Dual-target block register allocation	—	2007-12-11	$21,506,000
7246219	Methods and apparatus to control functional blocks within a processor	Andrew Shane Huang, Namratha Jaisimha	2007-07-17	$13,694,000
7080236	Updating stack pointer based on instruction bit indicator without executing an update microinstruction	Stephan Jourdan, Alan B. Kyker	2006-07-18	$11,508,000
7051190	Intra-instruction fusion	Stephen Jourdan	2006-05-23	$10,027,000
6907518	Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same	Jeffrey A. Lohman, Ram Gummadi	2005-06-14	$13,635,000
6889314	Method and apparatus for fast dependency coordinate matching	Murali Chinnakonda	2005-05-03	$20,343,000
6581155	Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same	Jeffrey A. Lohman, Ram Gummadi	2003-06-17	$18,116,000
6560671	Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses	Jacob Doweck	2003-05-06	$49,233,000
6519683	System and method for instruction cache re-ordering	Bradley Gene Burgess	2003-02-11	$38,289,000
6470435	Dual state rename recovery using register usage	Jacob Doweck, Belliappa Kuttanna	2002-10-22	$55,590,000
6412063	Multiple-operand instruction in a two operand pipeline and processor employing the same	—	2002-06-25
6275926	System and method for writing back multiple results over a single-result bus and processor employing the same	—	2001-08-14
5809530	Method and apparatus for processing multiple cache misses using reload folding and store merging	Betty Y. Kikuta	1998-09-15	$7,478,000
5765208	Method of speculatively executing store instructions prior to performing snoop operations	Jacqueline S. Nelson	1998-06-09	$8,396,000
5646878	Content addressable memory system	—	1997-07-08	$19,106,000
5448722	Method and system for data processing system error diagnosis utilizing hierarchical blackboard diagnostic sessions	Kenton J. Lynne, Thomas M. Walker	1995-09-05	$5,794,000

Nicholas Samra — 22 Patents

Issued Patents All Time

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