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Multi-die processor |
Bryan Black, M. Clair Webb |
2014-10-14 |
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Sleep state mechanism for virtual multithreading |
— |
2014-04-08 |
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Methods and apparatus to monitor instruction types and control power consumption within a processor |
Andrew Shane Huang, Namratha Jaisimha |
2012-07-10 |
| 7669203 |
Virtual multithreading translation mechanism including retrofit capability |
Andrew Shane Huang |
2010-02-23 |
| 7653904 |
System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected |
— |
2010-01-26 |
| 7398372 |
Fusing load and alu operations |
Stephan Jourdan, David J. Sager, Glenn J. Hinton |
2008-07-08 |
| 7308563 |
Dual-target block register allocation |
— |
2007-12-11 |
| 7246219 |
Methods and apparatus to control functional blocks within a processor |
Andrew Shane Huang, Namratha Jaisimha |
2007-07-17 |
| 7080236 |
Updating stack pointer based on instruction bit indicator without executing an update microinstruction |
Stephan Jourdan, Alan B. Kyker |
2006-07-18 |
| 7051190 |
Intra-instruction fusion |
Stephen Jourdan |
2006-05-23 |
| 6907518 |
Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same |
Jeffrey A. Lohman, Ram Gummadi |
2005-06-14 |
| 6889314 |
Method and apparatus for fast dependency coordinate matching |
Murali Chinnakonda |
2005-05-03 |
| 6581155 |
Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same |
Jeffrey A. Lohman, Ram Gummadi |
2003-06-17 |
| 6560671 |
Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses |
Jacob Doweck |
2003-05-06 |
| 6519683 |
System and method for instruction cache re-ordering |
Bradley Gene Burgess |
2003-02-11 |
| 6470435 |
Dual state rename recovery using register usage |
Jacob Doweck, Belliappa Kuttanna |
2002-10-22 |
| 6412063 |
Multiple-operand instruction in a two operand pipeline and processor employing the same |
— |
2002-06-25 |
| 6275926 |
System and method for writing back multiple results over a single-result bus and processor employing the same |
— |
2001-08-14 |
| 5809530 |
Method and apparatus for processing multiple cache misses using reload folding and store merging |
Betty Y. Kikuta |
1998-09-15 |
| 5765208 |
Method of speculatively executing store instructions prior to performing snoop operations |
Jacqueline S. Nelson |
1998-06-09 |
| 5646878 |
Content addressable memory system |
— |
1997-07-08 |
| 5448722 |
Method and system for data processing system error diagnosis utilizing hierarchical blackboard diagnostic sessions |
Kenton J. Lynne, Thomas M. Walker |
1995-09-05 |
