Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6370632 | Method and apparatus that enforces a regional memory model in hierarchical memory systems | James S. Blomgren, Terence M. Potter | 2002-04-09 |
| 6260131 | Method and apparatus for TLB memory ordering | James S. Blomgren, Terence M. Potter | 2001-07-10 |
| 5872949 | Apparatus and method for managing data flow dependencies arising from out-of-order execution, by an execution unit, of an instruction series input from an instruction source | Terence M. Potter | 1999-02-16 |
| 5809530 | Method and apparatus for processing multiple cache misses using reload folding and store merging | Nicholas Samra | 1998-09-15 |
| 5790443 | Mixed-modulo address generation using shadow segment registers | Gene W. Shen, Shalesh Thusoo, James S. Blomgren | 1998-08-04 |
| 5621896 | Data processor with unified store queue permitting hit under miss memory accesses | David P. Burgess, Milton M. Hood, Jr., Graham Ricketson Murphy | 1997-04-15 |