Issued Patents All Time
Showing 25 most recent of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9811875 | Texture state cache | Benjiman L. Goodman, Adam T. Moerschell | 2017-11-07 |
| 9652233 | Hint values for use with an operand cache | Terence M. Potter, Timothy A. Olson, Andrew M. Havlir, Michael A. Geary | 2017-05-16 |
| 9632785 | Instruction source specification | Terence M. Potter | 2017-04-25 |
| 9600288 | Result bypass cache | Terence M. Potter, Timothy A. Olson, Robert A. Drebin, Douglas C. Youngwith, Jon A. Loschke | 2017-03-21 |
| 9594395 | Clock routing techniques | Andrew M. Havlir, Terence M. Potter | 2017-03-14 |
| 9508112 | Multi-threaded GPU pipeline | Andrew M. Havlir, Terence M. Potter | 2016-11-29 |
| 9459869 | Intelligent caching for an operand cache | Timothy A. Olson, Terence M. Potter, Andrew M. Havlir | 2016-10-04 |
| 9442730 | Instruction source specification | Terence M. Potter | 2016-09-13 |
| 9417843 | Extended multiply | Terence M. Potter | 2016-08-16 |
| 9378146 | Operand cache design | Terence M. Potter, Timothy A. Olson, Andrew M. Havlir | 2016-06-28 |
| 9292285 | Interpolation implementation | — | 2016-03-22 |
| 9264066 | Type conversion using floating-point unit | Terence M. Potter | 2016-02-16 |
| 8482333 | Reduced voltage swing clock distribution | Michael E. Runas | 2013-07-09 |
| 7299461 | Expansion syntax | Fritz A. Boehm, Terence M. Potter | 2007-11-20 |
| 7219326 | Physical realization of dynamic logic using parameterized tile partitioning | Jeffrey B. Reed, Donald W. Glowka, Timothy A. Olson, Thomas W. Rudwick, III | 2007-05-15 |
| 7053664 | Null value propagation for FAST14 logic | Terence M. Potter | 2006-05-30 |
| 7031897 | Software modeling of logic signals capable of holding more than two values | Fritz A. Boehm | 2006-04-18 |
| 6956406 | Static storage element for dynamic logic | Michael R. Seningen, Terence M. Potter | 2005-10-18 |
| 6911846 | Method and apparatus for a 1 of N signal | Terence M. Potter, Stephen C. Horne, Michael R. Seningen, Anthony M. Petro | 2005-06-28 |
| 6898691 | Rearranging data between vector and matrix forms in a SIMD matrix processor | Timothy A. Olson, Christophe Harle | 2005-05-24 |
| 6745357 | Dynamic logic scan gate method and apparatus | David W. Chrudimsky, Stephen C. Horne, Michael R. Seningen | 2004-06-01 |
| 6714045 | Static transmission of FAST14 logic 1-of-N signals | Terence M. Potter, Laura Potter, Fritz A. Boehm | 2004-03-30 |
| 6622240 | Method and apparatus for pre-branch instruction | Timothy A. Olson | 2003-09-16 |
| 6604065 | Multiple-state simulation for non-binary logic | Fritz A. Boehm | 2003-08-05 |
| 6571378 | Method and apparatus for a N-NARY logic circuit using capacitance isolation | Terence M. Potter, Stephen C. Horne, Michael R. Seningen, Anthony M. Petro | 2003-05-27 |