Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10520249 | Process and apparatus for processing a hydrocarbon gas stream | — | 2019-12-31 |
| 9645721 | Device input modes with corresponding cover configurations | — | 2017-05-09 |
| 9405917 | Mechanism for protecting integrated circuits from security attacks | — | 2016-08-02 |
| 8837226 | Memory including a reduced leakage wordline driver | Edward M. McCombs, Alexander E. Runas, Daniel C. Chow | 2014-09-16 |
| 7026691 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence +2 more | 2006-04-11 |
| 6911846 | Method and apparatus for a 1 of N signal | James S. Blomgren, Terence M. Potter, Michael R. Seningen, Anthony M. Petro | 2005-06-28 |
| 6745357 | Dynamic logic scan gate method and apparatus | David W. Chrudimsky, James S. Blomgren, Michael R. Seningen | 2004-06-01 |
| 6732346 | Generation of route rules | Gopal Vijayan, Donald W. Glowka | 2004-05-04 |
| 6571378 | Method and apparatus for a N-NARY logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Michael R. Seningen, Anthony M. Petro | 2003-05-27 |
| 6445213 | Method for calculating dynamic logic block propagation delay targets using time borrowing | Gopal Vijayan, James S. Blomgren, Donald W. Glowka | 2002-09-03 |
| 6415405 | Method and apparatus for scan of synchronized dynamic logic using embedded scan gates | James S. Blomgren, Michael R. Seningen | 2002-07-02 |
| 6412085 | Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state | Kenneth D. Amstutz | 2002-06-25 |
| 6287953 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence +2 more | 2001-09-11 |
| 6288589 | Method and apparatus for generating clock signals | Terence M. Potter, James S. Blomgren, Anthony M. Petro | 2001-09-11 |
| 6271683 | Dynamic logic scan gate method and apparatus | James S. Blomgren, Michael R. Seningen | 2001-08-07 |
| 6268746 | Method and apparatus for logic synchronization | Terence M. Potter, James S. Blomgren, Anthony M. Petro | 2001-07-31 |
| 6252425 | Method and apparatus for an N-NARY logic circuit | James S. Blomgren, Terence M. Potter, Michael R. Seningen, Anthony M. Petro | 2001-06-26 |
| 6233707 | Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock | Terence M. Potter, James S. Blomgren, Anthony M. Petro | 2001-05-15 |
| 6191034 | Forming minimal size spaces in integrated circuit conductive lines | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee +1 more | 2001-02-20 |
| 6181596 | Method and apparatus for a RAM circuit having N-Nary output interface | Michael R. Seningen, James S. Blomgren | 2001-01-30 |
| 6146954 | Minimizing transistor size in integrated circuits | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence +2 more | 2000-11-14 |
| 6124735 | Method and apparatus for a N-nary logic circuit using capacitance isolation | James S. Blomgren, Terence M. Potter, Michael R. Seningen, Anthony M. Petro | 2000-09-26 |
| 6118304 | Method and apparatus for logic synchronization | Terence M. Potter, James S. Blomgren, Anthony M. Petro | 2000-09-12 |
| 6118716 | Method and apparatus for an address triggered RAM circuit | Michael R. Seningen, James S. Blomgren | 2000-09-12 |
| 6115294 | Method and apparatus for multi-bit register cell | James S. Blomgren, Terence M. Potter, Michael R. Seningen | 2000-09-05 |