| 7026691 |
Minimizing transistor size in integrated circuits |
Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee +2 more |
2006-04-11 |
$9,016,000 |
| 6287953 |
Minimizing transistor size in integrated circuits |
Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee +2 more |
2001-09-11 |
|
| 6274419 |
Trench isolation of field effect transistors |
Farrokh Omid-Zohoor, Andre Stolmeijer, Yowjuang W. Liu |
2001-08-14 |
$3,163,000 |
| 6146954 |
Minimizing transistor size in integrated circuits |
Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee +2 more |
2000-11-14 |
$4,365,000 |
| 6051881 |
Forming local interconnects in integrated circuits |
Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee +2 more |
2000-04-18 |
$8,077,000 |
| 6048652 |
Backside polish EUV mask and method of manufacture |
Khanh B. Nguyen |
2000-04-11 |
$13,721,000 |
| 6046088 |
Method for self-aligning polysilicon gates with field isolation and the resultant structure |
Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee +2 more |
2000-04-04 |
$6,962,000 |
| 5963816 |
Method for making shallow trench marks |
Larry Wang, Anna M. Minvielle |
1999-10-05 |
$1,787,000 |
| 5889697 |
Memory cell for storing at least three logic states |
Asim A. Selcuk |
1999-03-30 |
$2,138,000 |
| 5844836 |
Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell |
Nicholas J. Kepler, Asim A. Selcuk, Richard K. Klein, John C. Holst, Christopher A. Spence +2 more |
1998-12-01 |
$5,030,000 |
| 5777370 |
Trench isolation of field effect transistors |
Farrokh Omid-Zohoor, Andre Stolmeijer, Yowjuang W. Liu |
1998-07-07 |
$3,620,000 |
| 5136361 |
Stratified interconnect structure for integrated circuits |
Donald L. Wollesen, Jacob D. Haskell |
1992-08-04 |
$1,832,000 |
| 4962064 |
Method of planarization of topologies in integrated circuit structures |
Jacob D. Haskell, Steven C. Avanzino, Subhash Gupta |
1990-10-09 |
$943,000 |
| 4960732 |
Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
Pankaj Dixit, Jack Sliwa, Richard K. Klein, Mohammad Farnaam |
1990-10-02 |
$3,951,000 |
| 4951112 |
Triple-poly 4T static ram cell with two independent transistor gates |
Tat C. Choi, Richard K. Klein |
1990-08-21 |
$1,542,000 |
| 4912540 |
Reduced area butting contact structure |
Richard K. Klein, Tat C. Choi |
1990-03-27 |
$2,046,000 |
| 4884123 |
Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
Pankaj Dixit, Jack Sliwa, Richard K. Klein, Mohammad Farnaam |
1989-11-28 |
$2,481,000 |
| 4764800 |
Seal structure for an integrated circuit |
— |
1988-08-16 |
$2,671,000 |
| 4714686 |
Method of forming contact plugs for planarized integrated circuits |
Balaji Swaminathan |
1987-12-22 |
$1,961,000 |
| 4677589 |
Dynamic random access memory cell having a charge amplifier |
Jacob D. Haskell |
1987-06-30 |
$12,656,000 |
