Jacob D. Haskell — 34 Patents at AMD

Jacob D. Haskell has been granted 34 US patents while listed as an inventor at AMD. The first was granted in 1984 and the most recent in June 2009. Jacob D. Haskell ranks #100,737 of 4,157,543 US inventors in our database (top 2.4%). Patent records list Jacob D. Haskell in Palo Alto, CA, US.

Issued Patents All Time

Showing 1–25 of 34 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7541237	Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming	Jack Yuan	2009-06-02	$17,601,000
7288455	Method of forming non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors	Jack Yuan	2007-10-30	$21,432,000
6953964	Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming	Jack Yuan	2005-10-11	$32,157,000
6723604	Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming	Jack Yuan	2004-04-20	$54,890,000
6512263	Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming	Jack Yuan	2003-01-28	$19,061,000
6429132	Combination CMP-etch method for forming a thin planar layer over the surface of a device	Rong-Fu Hsu	2002-08-06
6297170	Sacrificial multilayer anti-reflective coating for mos gate formation	Calvin T. Gabriel, Satyendra Sethi	2001-10-02
6277748	Method for manufacturing a planar reflective light valve backplane	Rong-Fu Hsu	2001-08-21
6252999	Planar reflective light valve backplane	Rong-Fu Hsu	2001-06-26
6133635	Process for making self-aligned conductive via structures	Subhas Bothra	2000-10-17
6110818	Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof	—	2000-08-29
5776821	Method for forming a reduced width gate electrode	Satyendra Sethi, Calvin T. Gabriel	1998-07-07	$13,812,000
5395796	Etch stop layer using polymers for integrated circuits	Subhash Gupta	1995-03-07	$38,408,000
5198298	Etch stop layer using polymers	Subhash Gupta	1993-03-30	$9,779,000
5136361	Stratified interconnect structure for integrated circuits	Donald L. Wollesen, Craig S. Sander	1992-08-04	$1,832,000
5116778	Dopant sources for CMOS device	Steven C. Avanzino, Balaji Swaminathan	1992-05-26	$16,648,000
5091326	EPROM element employing self-aligning process	—	1992-02-25	$9,849,000
5081516	Self-aligned, planarized contacts for semiconductor devices	—	1992-01-14	$9,928,000
5057902	Self-aligned semiconductor devices	—	1991-10-15	$3,114,000
5055427	Process of forming self-aligned interconnects for semiconductor devices	—	1991-10-08	$11,737,000
5028555	Self-aligned semiconductor devices	—	1991-07-02	$14,022,000
4977108	Method of making self-aligned, planarized contacts for semiconductor devices	—	1990-12-11	$5,090,000
4974055	Self-aligned interconnects for semiconductor devices	—	1990-11-27	$4,158,000
4964143	EPROM element employing self-aligning process	—	1990-10-16	$1,736,000
4962064	Method of planarization of topologies in integrated circuit structures	Craig S. Sander, Steven C. Avanzino, Subhash Gupta	1990-10-09	$943,000

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Jacob D. Haskell — 34 Patents

Issued Patents All Time

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