AS

Andre Stolmeijer

AM AMD: 11 patents #1,098 of 9,279Top 15%
QU Quicklogic: 4 patents #18 of 70Top 30%
Cypress Semiconductor: 2 patents #733 of 1,852Top 40%
U.S. Philips: 2 patents #2,537 of 8,851Top 30%
Overall (All Time): #226,183 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6627969 Metal-to-metal antifuse having improved barrier layer Rajiv Jain, Mehul D. Shroff 2003-09-30
6274419 Trench isolation of field effect transistors Farrokh Omid-Zohoor, Yowjuang W. Liu, Craig S. Sander 2001-08-14
6232221 Borderless vias Khanh Tran, Sunil Mehta 2001-05-15
6154054 Programmable device having antifuses without programmable material edges and/or corners underneath metal Mehul D. Shroff, Rajiv Jain, Kathryn E. Gordon 2000-11-28
6127845 Field programmable gate array having internal logic transistors with two different gate insulator thicknesses Paige A. Kolze, David D. Eaton 2000-10-03
6107165 Metal-to-metal antifuse having improved barrier layer Rajiv Jain, Mehul D. Shroff 2000-08-22
6097090 High integrity vias Khanh Tran, Sunil Mehta 2000-08-01
5955751 Programmable device having antifuses without programmable material edges and/or corners underneath metal Mehul D. Shroff, Rajiv Jain, Kathryn E. Gordon 1999-09-21
5939766 High quality capacitor for sub-micrometer integrated circuits David C. Greenlaw 1999-08-17
5925932 Borderless vias Khanh Tran, Sunil Mehta 1999-07-20
5877066 Narrow width trenches for field isolation in integrated circuits Farrokh Omid-Zohoor 1999-03-02
5874317 Trench isolation for integrated circuits 1999-02-23
5834159 Image reversal technique for forming small structures in integrated circuits 1998-11-10
5834845 Interconnect scheme for integrated circuits 1998-11-10
5777370 Trench isolation of field effect transistors Farrokh Omid-Zohoor, Yowjuang W. Liu, Craig S. Sander 1998-07-07
5742090 Narrow width trenches for field isolation in integrated circuits Farrokh Omid-Zohoor 1998-04-21
5654915 6-bulk transistor static memory cell using split wordline architecture Christopher J. Petti 1997-08-05
5523258 Method for avoiding lithographic rounding effects for semiconductor fabrication Christopher J. Petti, Mark A. Helm 1996-06-04
5384279 Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations Paulus M. T. M. Van Attekum, Hubertus Den Blanken, Paulus A. Van Der Plas, Reinier De Werdt 1995-01-24
5081065 Method of contacting silicide tracks Alexander G. M. Jonkers, Christopher A. Seams, Harald Godon 1992-01-14