Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Khanh Tran — 45 Patents

AMD: 31 patents #313 of 9,280Top 4%
MPMaxim Integrated Products: 11 patents #42 of 945Top 5%
Xerox: 1 patents #5,237 of 8,622Top 65%
Intel: 1 patents #18,326 of 30,777Top 60%
Milpitas, CA: #80 of 3,192 inventorsTop 3%
California: #9,570 of 386,348 inventorsTop 3%
Overall (All Time): #64,393 of 4,157,543Top 2%
45 Patents All Time
Khanh Tran has been granted 45 US patents while listed as an inventor at AMD. The first was granted in 1996 and the most recent in October 2025. Khanh Tran ranks #64,393 of 4,157,543 US inventors in our database (top 1.5%). Patent records list Khanh Tran in Milpitas, CA, US.

Issued Patents All Time

Showing 1–25 of 45 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12436337 Low loss optical interposer Gabriel J. Mendoza, Wenguang Li, Vimal Kamineni, Mark Thompson 2025-10-07
10211172 Wafer-based electronic component packaging Anuranjan Srivastava 2019-02-19 $25,223,000
10056294 Techniques for adhesive control between a substrate and a die Vivek Swaminathan Sridharan, Srikanth Kulkarni 2018-08-21 $32,527,000
9882075 Light sensor with vertical diode junctions Nicole D. Kerness, Christopher F. Edwards, Joy T. Jones, Pirooz Parvarandeh 2018-01-30 $41,082,000
9704809 Fan-out and heterogeneous packaging of electronic components Arkadii V. Samoilov, Pirooz Parvarandeh, Amit S. Kelkar 2017-07-11 $13,657,000
9608130 Semiconductor device having trench capacitor structure integrated therein Joseph P. Ellul, Edward Martin Godshalk, Kiyoko Ikeuchi, Anuranjan Srivastava 2017-03-28 $10,085,000
9520462 Semiconductor device having capacitor integrated therein Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry 2016-12-13 $24,073,000
9196672 Semiconductor device having capacitor integrated therein Joseph P. Ellul, Anuranjan Srivastava, Kiyoko Ikeuchi, Scott W. Barry 2015-11-24 $9,611,000
8847365 Inductors and methods for integrated circuits Joseph P. Ellul, Edward Martin Godshalk, Albert Bergemont 2014-09-30 $19,269,000
8344478 Inductors having inductor axis parallel to substrate surface Joseph P. Ellul, Edward Martin Godshalk, Albert Bergemont 2013-01-01
8243021 Slide and rotate display configurations for a handheld computing device Rick Feightner, Wah Yiu Kwong, Katherine Mills, George K. Korinsky 2012-08-14 $13,822,000
7943473 Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme Joseph P. Ellul, Albert Bergemont 2011-05-17 $20,819,000
6607962 Globally planarized backend compatible thin film resistor contact/interconnect process Viktor Zekeriya 2003-08-19 $152,083,000
6522013 Punch-through via with conformal barrier liner Robert Chen, Jeffrey A. Shields, Robert Dawson 2003-02-18 $2,713,000
6492258 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY Minh Van Ngo, Paul R. Besser, Matthew S. Buynoski, John Caffall, Nick Maccrae +1 more 2002-12-10 $2,246,000
6472751 H2 diffusion barrier formation by nitrogen incorporation in oxide layer Robert Chen, Jeffrey A. Shields, Robert Dawson 2002-10-29 $1,498,000
6351013 Low-K sub spacer pocket formation for gate capacitance reduction Scott Luning, David Wu 2002-02-26 $4,948,000
6329718 Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Minh Van Ngo, Paul R. Besser, Matthew S. Buynoski, John Caffall, Nick Maccrae +1 more 2001-12-11 $6,262,000
6319859 Borderless vias with HSQ gap filled metal patterns having high etching resistance 2001-11-20 $3,380,000
6232221 Borderless vias Sunil Mehta, Andre Stolmeijer 2001-05-15 $7,906,000
6232223 High integrity borderless vias with protective sidewall spacer Sunil Mehta 2001-05-15 $7,906,000
6194328 H2 diffusion barrier formation by nitrogen incorporation in oxide layer Robert Chen, Jeffrey A. Shields, Robert Dawson 2001-02-27 $7,317,000
6163818 Streaming memory controller for a PCI bus Uoc H. Nguyen, Otto Sperber, David K. Bovaird 2000-12-19 $7,363,000
6133142 Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias Jeff Shields 2000-10-17 $7,276,000
6100179 Electromigration resistant patterned metal layer gap filled with HSQ 2000-08-08 $4,885,000