KT

Khanh Tran

AM AMD: 31 patents #304 of 9,279Top 4%
MP Maxim Integrated Products: 11 patents #42 of 945Top 5%
Xerox: 1 patents #5,237 of 8,622Top 65%
IN Intel: 1 patents #18,218 of 30,777Top 60%
📍 Milpitas, CA: #80 of 3,192 inventorsTop 3%
🗺 California: #9,798 of 386,348 inventorsTop 3%
Overall (All Time): #68,104 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
6093635 High integrity borderless vias with HSQ gap filled patterned conductive layers Richard J. Huang, Simon S. Chan, Lu You 2000-07-25
6087724 HSQ with high plasma etching resistance surface for borderless vias Jeffrey A. Shields, Robert Chen, Robert Dawson 2000-07-11
6083851 HSQ with high plasma etching resistance surface for borderless vias Jeffrey A. Shields, Robert Chen, Robert Dawson 2000-07-04
6060384 Borderless vias with HSQ gap filled patterned metal layers Robert Chen, Jeffrey A. Shields, Robert Dawson 2000-05-09
6046106 High density plasma oxide gap filled patterned metal layers with improved electromigration resistance Paul R. Besser, Guarionex Morales, Shekhar Pramanick 2000-04-04
6043147 Method of prevention of degradation of low dielectric constant gap-fill material Robert Chen, Jeffrey A. Shields, Robert Dawson 2000-03-28
6034420 Electromigration resistant patterned metal layer gap filled with HSQ 2000-03-07
6030891 Vacuum baked HSQ gap fill layer for high integrity borderless vias Richard J. Huang, Guarionex Morales 2000-02-29
6008116 Selective etching for improved dielectric interlayer planarization 1999-12-28
5990558 Reduced cracking in gap filling dielectrics 1999-11-23
5982035 High integrity borderless vias with protective sidewall spacer Sunil Mehta 1999-11-09
5973387 Tapered isolated metal profile to reduce dielectric layer cracking Robert Chen, Jeffrey A. Shields 1999-10-26
5942801 Borderless vias with HSQ gap filled metal patterns having high etching resistance 1999-08-24
5925932 Borderless vias Sunil Mehta, Andre Stolmeijer 1999-07-20
5888911 HSQ processing for reduced dielectric constant Minh Van Ngo, Lu You, Jean Y. Yang, Richard J. Huang 1999-03-30
5888898 HSQ baking for reduced dielectric constant Minh Van Ngo, Terri Jo Kitson, Lu You, Simon S. Chan, Jean Y. Yang 1999-03-30
5866945 Borderless vias with HSQ gap filled patterned metal layers Robert Chen, Jeffrey A. Shields, Robert Dawson 1999-02-02
5738917 Process for in-situ deposition of a Ti/TiN/Ti aluminum underlayer Paul R. Besser 1998-04-14
5582881 Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus Paul R. Besser, Raymond T. Lee 1996-12-10