Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7026691 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence +2 more | 2006-04-11 |
| 6479350 | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers | Zicheng Gary Ling, Todd P. Lukanc | 2002-11-12 |
| 6287904 | Two step mask process to eliminate gate end cap shortening | Zicheng Gary Ling | 2001-09-11 |
| 6287953 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence +2 more | 2001-09-11 |
| 6221706 | Aluminum disposable spacer to reduce mask count in CMOS transistor formation | Todd P. Lukanc, Zicheng Gary Ling, Matthew S. Buynoski | 2001-04-24 |
| 6218224 | Nitride disposable spacer to reduce mask count in CMOS transistor formation | Todd P. Lukanc, Zicheng Gary Ling | 2001-04-17 |
| 6214655 | Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation | Zicheng Gary Ling | 2001-04-10 |
| 6191034 | Forming minimal size spaces in integrated circuit conductive lines | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, John C. Holst +1 more | 2001-02-20 |
| 6166428 | Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon | Sunil Mehta, William G. En, Darin A. Chan | 2000-12-26 |
| 6146954 | Minimizing transistor size in integrated circuits | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence +2 more | 2000-11-14 |
| 6114235 | Multipurpose cap layer dielectric | David K. Foote, Minh Van Ngo, Christopher F. Lyons, Fei Wang, William G. En +2 more | 2000-09-05 |
| 6103563 | Nitride disposable spacer to reduce mask count in CMOS transistor formation | Todd P. Lukanc, Zicheng Gary Ling | 2000-08-15 |
| 6051881 | Forming local interconnects in integrated circuits | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence +2 more | 2000-04-18 |
| 6046088 | Method for self-aligning polysilicon gates with field isolation and the resultant structure | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence +2 more | 2000-04-04 |
| 5930659 | Forming minimal size spaces in integrated circuit conductive lines | Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, John C. Holst +1 more | 1999-07-27 |
| 5879980 | Method of making static random access memory cell having a trench field plate for increased capacitance | Asim A. Selcuk | 1999-03-09 |
| 5844836 | Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell | Nicholas J. Kepler, Asim A. Selcuk, Richard K. Klein, Craig S. Sander, John C. Holst +2 more | 1998-12-01 |
| 5796651 | Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device | Stephen C. Horne, Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence +1 more | 1998-08-18 |
| 5674781 | Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application | Richard J. Huang, Robin Cheung, Rajat Rakkhit | 1997-10-07 |
| 5654589 | Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application | Richard J. Huang, Robin Cheung, Rajat Rakkhit | 1997-08-05 |
| 5627110 | Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used | Richard K. Klein | 1997-05-06 |
| 5582881 | Process for deposition of a Ti/TiN cap layer on aluminum metallization and apparatus | Paul R. Besser, Khanh Tran | 1996-12-10 |