Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7026691 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee +2 more | 2006-04-11 |
| 6475868 | Oxygen implantation for reduction of junction capacitance in MOS transistors | Ming-Yin Hao, Richard P. Rouse, Emi Ishida | 2002-11-05 |
| 6383827 | Electrical alignment test structure using local interconnect ladder resistor | Todd P. Lukanc | 2002-05-07 |
| 6306738 | Modulation of gate polysilicon doping profile by sidewall implantation | — | 2001-10-23 |
| 6291864 | Gate structure having polysilicon layer with recessed side portions | — | 2001-09-18 |
| 6287953 | Minimizing transistor size in integrated circuits | Craig S. Sander, Rich Klein, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee +2 more | 2001-09-11 |
| 6200864 | Method of asymmetrically doping a region beneath a gate | — | 2001-03-13 |
| 6191034 | Forming minimal size spaces in integrated circuit conductive lines | Richard K. Klein, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst +1 more | 2001-02-20 |
| 6165882 | Polysilicon gate having a metal plug, for reduced gate resistance, within a trench extending into the polysilicon layer of the gate | — | 2000-12-26 |
| 6146954 | Minimizing transistor size in integrated circuits | Richard K. Klein, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee +2 more | 2000-11-14 |
| 6130470 | Static random access memory cell having buried sidewall capacitors between storage nodes | — | 2000-10-10 |
| 6051881 | Forming local interconnects in integrated circuits | Richard K. Klein, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee +2 more | 2000-04-18 |
| 6046088 | Method for self-aligning polysilicon gates with field isolation and the resultant structure | Richard K. Klein, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee +2 more | 2000-04-04 |
| 5981995 | Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes | — | 1999-11-09 |
| 5930659 | Forming minimal size spaces in integrated circuit conductive lines | Richard K. Klein, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst +1 more | 1999-07-27 |
| 5889697 | Memory cell for storing at least three logic states | Craig S. Sander | 1999-03-30 |
| 5879980 | Method of making static random access memory cell having a trench field plate for increased capacitance | Raymond T. Lee | 1999-03-09 |
| 5844836 | Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell | Nicholas J. Kepler, Richard K. Klein, Craig S. Sander, John C. Holst, Christopher A. Spence +2 more | 1998-12-01 |
| 5796651 | Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device | Stephen C. Horne, Richard K. Klein, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee +1 more | 1998-08-18 |
| 5793671 | Static random access memory cell utilizing enhancement mode N-channel transistors as load elements | — | 1998-08-11 |
| 4905065 | High density dram trench capacitor isolation employing double epitaxial layers | Pau-Ling Chen, Darrell M. Erb | 1990-02-27 |
| 4650544 | Shallow groove capacitor fabrication method | Darrell M. Erb | 1987-03-17 |