Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DC

Darin A. Chan — 41 Patents

AMD: 33 patents #294 of 9,280Top 4%
GPGlobalfoundries Singapore Pte.: 6 patents #123 of 828Top 15%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Santa Clara, CA: #306 of 9,301 inventorsTop 4%
California: #11,075 of 386,348 inventorsTop 3%
Overall (All Time): #75,001 of 4,157,543Top 2%
41 Patents All Time
Darin A. Chan has been granted 41 US patents while listed as an inventor at AMD. The first was granted in 1995 and the most recent in January 2023. Darin A. Chan ranks #75,001 of 4,157,543 US inventors in our database (top 1.8%). Patent records list Darin A. Chan in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–25 of 41 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11545570 High-voltage devices integrated on semiconductor-on-insulator substrate Pinghui Li, Handoko Linewih, Ruchil Kumar Jain 2023-01-03
10978510 Memory device with density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu +1 more 2021-04-13
10374005 Density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology and method for producing the same Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu +1 more 2019-08-06
9825185 Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures Pinghui Li, Ming Zhu, Xinshu Cai, Fan Zhang, Danny Pak-Chum Shum 2017-11-21
9780231 Integrated circuits with flash memory and methods for producing the same Pinghui Li, Ming Zhu, Danny Pak-Chum Shum, Xinshu Cai 2017-10-03
9698200 Magnetism-controllable dummy structures in memory device Pinghui Li, Ming Zhu, Shunqiang Gong, Wanbing Yi, Yiang Aun Nga 2017-07-04
8293606 Body tie test structure for accurate body effect measurement Sriram Madhavan, Qiang Chen, Jung-Suk Goo 2012-10-23 $1,510,000
7880229 Body tie test structure for accurate body effect measurement Sriram Madhavan, Qiang Chen, Jung-Suk Goo 2011-02-01 $4,279,000
7861195 Process for design of semiconductor circuits Yi Zou, Yuansheng Ma, Marilyn I. Wright, Mark W. Michael 2010-12-28 $4,143,000
7494885 Disposable spacer process for field effect transistor fabrication Mario M. Pelella, Kei-Leong Ho, Lu You 2009-02-24 $4,276,000
7465623 Methods for fabricating a semiconductor device on an SOI substrate Mario M. Pelella 2008-12-16 $5,569,000
7276755 Integrated circuit and method of manufacture 2007-10-02 $16,573,000
7250667 Selectable open circuit and anti-fuse element Simon S. Chan, Paul L. King 2007-07-31 $9,995,000
7223640 Semiconductor component and method of manufacture Mario M. Pelella, Simon S. Chan 2007-05-29 $8,835,000
7151020 Conversion of transition metal to silicide through back end processing in integrated circuit technology Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan +3 more 2006-12-19 $26,185,000
7023059 Trenches to reduce lateral silicide growth in integrated circuit technology Simon S. Chan, Jeffrey P. Patton, Jacques Bertrand 2006-04-04 $14,413,000
7015076 Selectable open circuit and anti-fuse element, and fabrication method therefor Simon S. Chan, Paul L. King 2006-03-21 $13,217,000
6812077 Method for patterning narrow gate lines Douglas J. Bonser, Mark S. Chang 2004-11-02 $2,431,000
6780776 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer Wen-Jie Qi, John G. Pellerin, William G. En, Mark W. Michael 2004-08-24 $2,825,000
6764949 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Douglas J. Bonser, Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Philip A. Fisher +6 more 2004-07-20 $1,607,000
6764947 Method for reducing gate line deformation and reducing gate line widths in semiconductor devices Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih-Yuh Yang, Lu You +2 more 2004-07-20 $1,607,000
6764917 SOI device with different silicon thicknesses William G. En, John G. Pellerin, Mark W. Michael 2004-07-20 $1,607,000
6750127 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance Mark S. Chang, Chih-Yuh Yang, Lu You, Scott A. Bell, Srikanteswara Dakshina-Murthy +1 more 2004-06-15 $4,556,000
6566176 SOI device with wrap-around contact to underside of body, and method of making 2003-05-20 $2,116,000
6521510 Method for shallow trench isolation with removal of strained island edges Philip A. Fisher 2003-02-18 $2,713,000