Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11545570 | High-voltage devices integrated on semiconductor-on-insulator substrate | Pinghui Li, Handoko Linewih, Ruchil Kumar Jain | 2023-01-03 |
| 10978510 | Memory device with density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology | Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu +1 more | 2021-04-13 |
| 10374005 | Density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology and method for producing the same | Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu +1 more | 2019-08-06 |
| 9825185 | Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures | Pinghui Li, Ming Zhu, Xinshu Cai, Fan Zhang, Danny Pak-Chum Shum | 2017-11-21 |
| 9780231 | Integrated circuits with flash memory and methods for producing the same | Pinghui Li, Ming Zhu, Danny Pak-Chum Shum, Xinshu Cai | 2017-10-03 |
| 9698200 | Magnetism-controllable dummy structures in memory device | Pinghui Li, Ming Zhu, Shunqiang Gong, Wanbing Yi, Yiang Aun Nga | 2017-07-04 |
| 8293606 | Body tie test structure for accurate body effect measurement | Sriram Madhavan, Qiang Chen, Jung-Suk Goo | 2012-10-23 |
| 7880229 | Body tie test structure for accurate body effect measurement | Sriram Madhavan, Qiang Chen, Jung-Suk Goo | 2011-02-01 |
| 7861195 | Process for design of semiconductor circuits | Yi Zou, Yuansheng Ma, Marilyn I. Wright, Mark W. Michael | 2010-12-28 |
| 7494885 | Disposable spacer process for field effect transistor fabrication | Mario M. Pelella, Kei-Leong Ho, Lu You | 2009-02-24 |
| 7465623 | Methods for fabricating a semiconductor device on an SOI substrate | Mario M. Pelella | 2008-12-16 |
| 7276755 | Integrated circuit and method of manufacture | — | 2007-10-02 |
| 7250667 | Selectable open circuit and anti-fuse element | Simon S. Chan, Paul L. King | 2007-07-31 |
| 7223640 | Semiconductor component and method of manufacture | Mario M. Pelella, Simon S. Chan | 2007-05-29 |
| 7151020 | Conversion of transition metal to silicide through back end processing in integrated circuit technology | Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan +3 more | 2006-12-19 |
| 7023059 | Trenches to reduce lateral silicide growth in integrated circuit technology | Simon S. Chan, Jeffrey P. Patton, Jacques Bertrand | 2006-04-04 |
| 7015076 | Selectable open circuit and anti-fuse element, and fabrication method therefor | Simon S. Chan, Paul L. King | 2006-03-21 |
| 6812077 | Method for patterning narrow gate lines | Douglas J. Bonser, Mark S. Chang | 2004-11-02 |
| 6780776 | Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer | Wen-Jie Qi, John G. Pellerin, William G. En, Mark W. Michael | 2004-08-24 |
| 6764949 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Douglas J. Bonser, Marina V. Plat, Chih-Yuh Yang, Scott A. Bell, Philip A. Fisher +6 more | 2004-07-20 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices | Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Chih-Yuh Yang, Lu You +2 more | 2004-07-20 |
| 6764917 | SOI device with different silicon thicknesses | William G. En, John G. Pellerin, Mark W. Michael | 2004-07-20 |
| 6750127 | Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance | Mark S. Chang, Chih-Yuh Yang, Lu You, Scott A. Bell, Srikanteswara Dakshina-Murthy +1 more | 2004-06-15 |
| 6566176 | SOI device with wrap-around contact to underside of body, and method of making | — | 2003-05-20 |
| 6521510 | Method for shallow trench isolation with removal of strained island edges | Philip A. Fisher | 2003-02-18 |