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USPTO Patent Rankings Data through Dec 31, 2025
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Robert J. Chiu — 13 Patents

AMD: 11 patents #1,153 of 9,280Top 15%
SLSpansion Llc.: 2 patents #309 of 769Top 45%
Cypress Semiconductor: 1 patents #1,072 of 1,852Top 60%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
San Jose, CA: #5,025 of 32,062 inventorsTop 20%
California: #47,433 of 386,348 inventorsTop 15%
Overall (All Time): #362,438 of 4,157,543Top 9%
13 Patents All Time
Robert J. Chiu has been granted 13 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in March 2016. Robert J. Chiu ranks #362,438 of 4,157,543 US inventors in our database (top 8.7%). Patent records list Robert J. Chiu in San Jose, CA, US.

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9299643 Ruthenium interconnect with high aspect ratio and method of fabrication thereof Zheng Wang, Connie P. Wang, Erik Wilson, Wen Yu 2016-03-29 $5,372,000
7843015 Multi-silicide system in integrated circuit technology Paul R. Besser, Simon S. Chan, Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler +1 more 2010-11-30 $11,033,000
7670915 Contact liner in integrated circuit technology Errol Todd Ryan, Paul R. Besser, Simon S. Chan, Mehrdad Mahanpour, Minh Van Ngo 2010-03-02 $5,781,000
7468296 Thin film germanium diode with low reverse breakdown Ercan Adem, Matthew S. Buynoski, Bryan K. Choo, Calvin T. Gabriel, Joong S. Jeon +5 more 2008-12-23
7378310 Method for manufacturing a memory device having a nanocrystal charge storage region Connie P. Wang, Zoran Krivokapic, Suzette K. Pangrle, Lu You 2008-05-27
7307322 Ultra-uniform silicide system in integrated circuit technology Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo 2007-12-11 $6,596,000
7151020 Conversion of transition metal to silicide through back end processing in integrated circuit technology Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler, Errol Todd Ryan, Darin A. Chan +3 more 2006-12-19 $26,185,000
7049666 Low power pre-silicide process in integrated circuit technology Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo 2006-05-23 $17,017,000
7005357 Low stress sidewall spacer in integrated circuit technology Minh Van Ngo, Simon S. Chan, Paul R. Besser, Paul L. King, Errol Todd Ryan 2006-02-28 $11,043,000
7005376 Ultra-uniform silicides in integrated circuit technology Jeffrey P. Patton, Paul R. Besser, Minh Van Ngo 2006-02-28 $11,043,000
6969678 Multi-silicide in integrated circuit technology Paul R. Besser, Simon S. Chan, Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler +1 more 2005-11-29 $10,680,000
6576548 Method of manufacturing a semiconductor device with reliable contacts/vias Amy C. Tu, Minh Van Ngo, Austin Frenkel, Jeff P. Erhardt 2003-06-10 $2,757,000
6171737 Low cost application of oxide test wafer for defect monitor in photolithography process Khoi A. Phan, Shobhana Punjabi, Bhanwar Singh 2001-01-09 $4,016,000