Jeff P. Erhardt — 17 Patents at AMD

Jeff P. Erhardt has been granted 17 US patents while listed as an inventor at AMD. The first was granted in 2002 and the most recent in January 2009. Jeff P. Erhardt ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Jeff P. Erhardt in San Jose, CA, US.

Patents per Year

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Showing 1–17 of 17 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7476604	Aggressive cleaning process for semiconductor device contact formation	Ning Cheng, Minh Van Ngo, Jinsong Yin, Paul R. Besser, Connie P. Wang +4 more	2009-01-13
7118967	Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing	Minh Van Ngo, Ning Cheng, Clarence B. Ferguson, Cyrus E. Tabery, John Caffall +2 more	2006-10-10	$5,547,000
7018868	Disposable hard mask for memory bitline scaling	Jean Y. Yang, Cyrus E. Tabery, Weidong Qian, Mark T. Ramsbey, Jaeyong Park +1 more	2006-03-28	$11,294,000
7018896	UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing	Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more	2006-03-28	$11,294,000
6987048	Memory device having silicided bitlines and method of forming the same	Ning Cheng, Hiroyuki Kinoshita, Mark T. Ramsbey, Cyrus E. Tabery, Jean Y. Yang	2006-01-17	$20,825,000
6963108	Recessed channel	Inkuk Kang, Hiroyuki Kinoshita, Emmanuil H. Lingunis	2005-11-08	$6,799,000
6855608	Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance	Mark T. Ramsbey, Mark Randolph, Jean Y. Yang, Hiroyuki Kinoshita, Cyrus E. Tabery +3 more	2005-02-15	$5,967,000
6835662	Partially de-coupled core and periphery gate module process	Hiroyuki Kinoshita, Cyrus E. Tabery	2004-12-28	$7,308,000
6774432	UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL	Minh Van Ngo, Tazrien Kamal, Mark T. Ramsbey, Arvind Halliyal, Jaeyong Park +6 more	2004-08-10	$1,968,000
6744105	Memory array having shallow bit line with silicide contact portion and method of formation	Cinti X. Chen, Hiroyuki Kinoshita, Weidong Qian, Jean Y. Yang	2004-06-01	$2,717,000
6613500	Reducing resist residue defects in open area on patterned wafer using trim mask	Khoi A. Phan, Bhanwar Singh, Ramkumar Subramanian, Michael K. Templeton	2003-09-02	$4,831,000
6576548	Method of manufacturing a semiconductor device with reliable contacts/vias	Amy C. Tu, Minh Van Ngo, Austin Frenkel, Robert J. Chiu	2003-06-10	$2,757,000
6521501	Method of forming a CMOS transistor having ultra shallow source and drain regions	Bin Yu, G. Jonathan Kluth	2003-02-18	$2,713,000
6514859	Method of salicide formation with a double gate silicide	Eric N. Paton	2003-02-04	$1,030,000
6513151	Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation	Khoi A. Phan	2003-01-28	$2,528,000
6399467	Method of salicide formation	Eric N. Paton	2002-06-04	$2,015,000
6387786	Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area	Eric N. Paton	2002-05-14	$2,737,000

Jeff P. Erhardt — 17 Patents

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